Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Treat both operands as signed values for
	"div" instruction.

	* simops.c: Fix simulation of division instructions.
	Fix typos/thinkos in several "cmp" and "sub" instructions.

Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Fix carry bit handling in "sub" and "cmp"
	instructions.

	* simops.c: Fix "mov imm8,an" and "mov imm16,dn".

Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Fix overflow computation for many instructions.

	* simops.c: Fix "movdm, an", "movbu dm, (an)", and "movhu dm, (an)".

	* simops.c: Fix "mov am, dn".

	* simops.c: Fix more bugs in "add imm,an" and
	"add imm,dn".

Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Fix bugs in "movm" and "add imm,an".

	* simops.c: Don't lose the upper 24 bits of the return
	pointer in "call" and "calls" instructions.  Rough cut
	at emulated system calls.

	* simops.c: Implement the remaining 5, 6 and 7 byte instructions.

	* simops.c: Implement remaining 4 byte instructions.

	* simops.c: Implement remaining 3 byte instructions.

	* simops.c: Implement remaining 2 byte instructions.  Call
	abort for instructions we're not implementing now.

Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Implement lots of random instructions.

	* simops.c: Implement "movm" and "bCC" insns.

	* mn10300_sim.h (_state): Add another register (MDR).
	(REG_MDR): Define.
	* simops.c: Implement "cmp", "calls", "rets", "jmp" and
	a few additional random insns.

	* mn10300_sim.h (PSW_*): Define for CC status tracking.
	(REG_D0, REG_A0, REG_SP): Define.
	* simops.c: Implement "add", "addc" and a few other random
	instructions.

	* gencode.c, interp.c: Snapshot current simulator code.

Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)

	* Makefile.in, config.in, configure, configure.in: New files.
	* gencode.c, interp.c, mn10300_sim.h, simops.c: New files.