+
+/* Unused Reloc */
+ BFD_RELOC_MICROBLAZE_64_TLS,
+
+/* This is a 64 bit reloc that stores the 32 bit GOT relative value
+of the GOT TLS GD info entry in two words (with an imm instruction). The
+relocation is GOT offset. */
+ BFD_RELOC_MICROBLAZE_64_TLSGD,
+
+/* This is a 64 bit reloc that stores the 32 bit GOT relative value
+of the GOT TLS LD info entry in two words (with an imm instruction). The
+relocation is GOT offset. */
+ BFD_RELOC_MICROBLAZE_64_TLSLD,
+
+/* This is a 32 bit reloc that stores the Module ID to GOT(n). */
+ BFD_RELOC_MICROBLAZE_32_TLSDTPMOD,
+
+/* This is a 32 bit reloc that stores TLS offset to GOT(n+1). */
+ BFD_RELOC_MICROBLAZE_32_TLSDTPREL,
+
+/* This is a 32 bit reloc for storing TLS offset to two words (uses imm
+instruction) */
+ BFD_RELOC_MICROBLAZE_64_TLSDTPREL,
+
+/* This is a 64 bit reloc that stores 32-bit thread pointer relative offset
+to two words (uses imm instruction). */
+ BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL,
+
+/* This is a 64 bit reloc that stores 32-bit thread pointer relative offset
+to two words (uses imm instruction). */
+ BFD_RELOC_MICROBLAZE_64_TLSTPREL,
+
+/* AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
+Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_ADD_LO12,
+
+/* AArch64 Load Literal instruction, holding a 19 bit PC relative word
+offset of the global offset table entry for a symbol. The lowest two
+bits must be zero and are not stored in the instruction, giving a 21
+bit signed byte offset. This relocation type requires signed overflow
+checking. */
+ BFD_RELOC_AARCH64_GOT_LD_PREL19,
+
+/* Get to the page base of the global offset table entry for a symbol as
+part of an ADRP instruction using a 21 bit PC relative value.Used in
+conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. */
+ BFD_RELOC_AARCH64_ADR_GOT_PAGE,
+
+/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+offset, giving a 4KB aligned page base address. */
+ BFD_RELOC_AARCH64_ADR_HI21_PCREL,
+
+/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+offset, giving a 4KB aligned page base address, but with no overflow
+checking. */
+ BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
+
+/* AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. */
+ BFD_RELOC_AARCH64_ADR_LO21_PCREL,
+
+/* AArch64 19 bit pc-relative conditional branch and compare & branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 21 bit signed byte offset. */
+ BFD_RELOC_AARCH64_BRANCH19,
+
+/* AArch64 26 bit pc-relative unconditional branch and link.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 28 bit signed byte offset. */
+ BFD_RELOC_AARCH64_CALL26,
+
+/* AArch64 pseudo relocation code to be used internally by the AArch64
+assembler and not (currently) written to any object files. */
+ BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP,
+
+/* AArch64 26 bit pc-relative unconditional branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 28 bit signed byte offset. */
+ BFD_RELOC_AARCH64_JUMP26,
+
+/* AArch64 Load Literal instruction, holding a 19 bit pc-relative word
+offset. The lowest two bits must be zero and are not stored in the
+instruction, giving a 21 bit signed byte offset. */
+ BFD_RELOC_AARCH64_LD_LO19_PCREL,
+
+/* Unsigned 12 bit byte offset for 64 bit load/store from the page of
+the GOT entry for this symbol. Used in conjunction with
+BFD_RELOC_AARCH64_ADR_GOTPAGE. */
+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC,
+
+/* AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST_LO12,
+
+/* AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST8_LO12,
+
+/* AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST16_LO12,
+
+/* AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST32_LO12,
+
+/* AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST64_LO12,
+
+/* AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST128_LO12,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 0 to 15
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G0,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G0_S,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
+an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G0_NC,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 16 to 31
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G1,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 16 to 31
+of an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G1_NC,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 16 to 31
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G1_S,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 32 to 47
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G2,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 32 to 47
+of an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G2_NC,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 32 to 47
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G2_S,
+
+/* AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
+of a signed or unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G3,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLSDESC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADD,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_CALL,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LDR,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
+
+/* Unsigned 12 bit byte offset to global offset table entry for a symbols
+tls_index structure. Used in conjunction with
+BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. */
+ BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
+
+/* Get to the page base of the global offset table entry for a symbols
+tls_index structure as part of an adrp instruction using a 21 bit PC
+relative value. Used in conjunction with
+BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. */
+ BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_DTPMOD64,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_DTPREL64,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_TPREL64,
+
+/* AArch64 14 bit pc-relative test bit and branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 16 bit signed byte offset. */
+ BFD_RELOC_AARCH64_TSTBR14,
+
+/* Tilera TILEPro Relocations. */
+ BFD_RELOC_TILEPRO_COPY,
+ BFD_RELOC_TILEPRO_GLOB_DAT,
+ BFD_RELOC_TILEPRO_JMP_SLOT,
+ BFD_RELOC_TILEPRO_RELATIVE,
+ BFD_RELOC_TILEPRO_BROFF_X1,
+ BFD_RELOC_TILEPRO_JOFFLONG_X1,
+ BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT,
+ BFD_RELOC_TILEPRO_IMM8_X0,
+ BFD_RELOC_TILEPRO_IMM8_Y0,
+ BFD_RELOC_TILEPRO_IMM8_X1,
+ BFD_RELOC_TILEPRO_IMM8_Y1,
+ BFD_RELOC_TILEPRO_DEST_IMM8_X1,
+ BFD_RELOC_TILEPRO_MT_IMM15_X1,
+ BFD_RELOC_TILEPRO_MF_IMM15_X1,
+ BFD_RELOC_TILEPRO_IMM16_X0,
+ BFD_RELOC_TILEPRO_IMM16_X1,
+ BFD_RELOC_TILEPRO_IMM16_X0_LO,
+ BFD_RELOC_TILEPRO_IMM16_X1_LO,
+ BFD_RELOC_TILEPRO_IMM16_X0_HI,
+ BFD_RELOC_TILEPRO_IMM16_X1_HI,
+ BFD_RELOC_TILEPRO_IMM16_X0_HA,
+ BFD_RELOC_TILEPRO_IMM16_X1_HA,
+ BFD_RELOC_TILEPRO_IMM16_X0_PCREL,
+ BFD_RELOC_TILEPRO_IMM16_X1_PCREL,
+ BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL,
+ BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL,
+ BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL,
+ BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL,
+ BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL,
+ BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL,
+ BFD_RELOC_TILEPRO_IMM16_X0_GOT,
+ BFD_RELOC_TILEPRO_IMM16_X1_GOT,
+ BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO,
+ BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO,
+ BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI,
+ BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI,
+ BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA,
+ BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA,
+ BFD_RELOC_TILEPRO_MMSTART_X0,
+ BFD_RELOC_TILEPRO_MMEND_X0,
+ BFD_RELOC_TILEPRO_MMSTART_X1,
+ BFD_RELOC_TILEPRO_MMEND_X1,
+ BFD_RELOC_TILEPRO_SHAMT_X0,
+ BFD_RELOC_TILEPRO_SHAMT_X1,
+ BFD_RELOC_TILEPRO_SHAMT_Y0,
+ BFD_RELOC_TILEPRO_SHAMT_Y1,
+ BFD_RELOC_TILEPRO_TLS_GD_CALL,
+ BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD,
+ BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD,
+ BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD,
+ BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD,
+ BFD_RELOC_TILEPRO_TLS_IE_LOAD,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA,
+ BFD_RELOC_TILEPRO_TLS_DTPMOD32,
+ BFD_RELOC_TILEPRO_TLS_DTPOFF32,
+ BFD_RELOC_TILEPRO_TLS_TPOFF32,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA,
+
+/* Tilera TILE-Gx Relocations. */
+ BFD_RELOC_TILEGX_HW0,
+ BFD_RELOC_TILEGX_HW1,
+ BFD_RELOC_TILEGX_HW2,
+ BFD_RELOC_TILEGX_HW3,
+ BFD_RELOC_TILEGX_HW0_LAST,
+ BFD_RELOC_TILEGX_HW1_LAST,
+ BFD_RELOC_TILEGX_HW2_LAST,
+ BFD_RELOC_TILEGX_COPY,
+ BFD_RELOC_TILEGX_GLOB_DAT,
+ BFD_RELOC_TILEGX_JMP_SLOT,
+ BFD_RELOC_TILEGX_RELATIVE,
+ BFD_RELOC_TILEGX_BROFF_X1,
+ BFD_RELOC_TILEGX_JUMPOFF_X1,
+ BFD_RELOC_TILEGX_JUMPOFF_X1_PLT,
+ BFD_RELOC_TILEGX_IMM8_X0,
+ BFD_RELOC_TILEGX_IMM8_Y0,
+ BFD_RELOC_TILEGX_IMM8_X1,
+ BFD_RELOC_TILEGX_IMM8_Y1,
+ BFD_RELOC_TILEGX_DEST_IMM8_X1,
+ BFD_RELOC_TILEGX_MT_IMM14_X1,
+ BFD_RELOC_TILEGX_MF_IMM14_X1,
+ BFD_RELOC_TILEGX_MMSTART_X0,
+ BFD_RELOC_TILEGX_MMEND_X0,
+ BFD_RELOC_TILEGX_SHAMT_X0,
+ BFD_RELOC_TILEGX_SHAMT_X1,
+ BFD_RELOC_TILEGX_SHAMT_Y0,
+ BFD_RELOC_TILEGX_SHAMT_Y1,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1,
+ BFD_RELOC_TILEGX_IMM16_X0_HW2,
+ BFD_RELOC_TILEGX_IMM16_X1_HW2,
+ BFD_RELOC_TILEGX_IMM16_X0_HW3,
+ BFD_RELOC_TILEGX_IMM16_X1_HW3,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST,
+ BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST,
+ BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT,
+ BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE,
+ BFD_RELOC_TILEGX_TLS_DTPMOD64,
+ BFD_RELOC_TILEGX_TLS_DTPOFF64,
+ BFD_RELOC_TILEGX_TLS_TPOFF64,
+ BFD_RELOC_TILEGX_TLS_DTPMOD32,
+ BFD_RELOC_TILEGX_TLS_DTPOFF32,
+ BFD_RELOC_TILEGX_TLS_TPOFF32,
+ BFD_RELOC_TILEGX_TLS_GD_CALL,
+ BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD,
+ BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD,
+ BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD,
+ BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD,
+ BFD_RELOC_TILEGX_TLS_IE_LOAD,
+ BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD,
+ BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD,
+ BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD,
+ BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD,
+
+/* Adapteva EPIPHANY - 8 bit signed pc-relative displacement */
+ BFD_RELOC_EPIPHANY_SIMM8,
+
+/* Adapteva EPIPHANY - 24 bit signed pc-relative displacement */
+ BFD_RELOC_EPIPHANY_SIMM24,
+
+/* Adapteva EPIPHANY - 16 most-significant bits of absolute address */
+ BFD_RELOC_EPIPHANY_HIGH,
+
+/* Adapteva EPIPHANY - 16 least-significant bits of absolute address */
+ BFD_RELOC_EPIPHANY_LOW,
+
+/* Adapteva EPIPHANY - 11 bit signed number - add/sub immediate */
+ BFD_RELOC_EPIPHANY_SIMM11,
+
+/* Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) */
+ BFD_RELOC_EPIPHANY_IMM11,
+
+/* Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. */
+ BFD_RELOC_EPIPHANY_IMM8,