+ bfd_get_mach (ibfd)))
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+/* This function handles relaxing for the H8..
+
+ There are a few relaxing opportunities available on the H8:
+
+ jmp/jsr:24 -> bra/bsr:8 2 bytes
+ The jmp may be completely eliminated if the previous insn is a
+ conditional branch to the insn after the jump. In that case
+ we invert the branch and delete the jump and save 4 bytes.
+
+ bCC:16 -> bCC:8 2 bytes
+ bsr:16 -> bsr:8 2 bytes
+
+ bset:16 -> bset:8 2 bytes
+ bset:24/32 -> bset:8 4 bytes
+ (also applicable to other bit manipulation instructions)
+
+ mov.b:16 -> mov.b:8 2 bytes
+ mov.b:24/32 -> mov.b:8 4 bytes
+
+ bset:24/32 -> bset:16 2 bytes
+ (also applicable to other bit manipulation instructions)
+
+ mov.[bwl]:24/32 -> mov.[bwl]:16 2 bytes
+
+ mov.[bwl] @(displ:24/32+ERx) -> mov.[bwl] @(displ:16+ERx) 4 bytes. */
+
+static bfd_boolean
+elf32_h8_relax_section (bfd *abfd, asection *sec,
+ struct bfd_link_info *link_info, bfd_boolean *again)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ Elf_Internal_Rela *internal_relocs;
+ Elf_Internal_Rela *irel, *irelend;
+ bfd_byte *contents = NULL;
+ Elf_Internal_Sym *isymbuf = NULL;
+ static asection *last_input_section = NULL;
+ static Elf_Internal_Rela *last_reloc = NULL;
+
+ /* Assume nothing changes. */
+ *again = FALSE;
+
+ /* We don't have to do anything for a relocatable link, if
+ this section does not have relocs, or if this is not a
+ code section. */
+ if (bfd_link_relocatable (link_info)
+ || (sec->flags & SEC_RELOC) == 0
+ || sec->reloc_count == 0
+ || (sec->flags & SEC_CODE) == 0)
+ return TRUE;
+
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+
+ /* Get a copy of the native relocations. */
+ internal_relocs = (_bfd_elf_link_read_relocs
+ (abfd, sec, NULL, (Elf_Internal_Rela *) NULL,
+ link_info->keep_memory));
+ if (internal_relocs == NULL)
+ goto error_return;
+
+ if (sec != last_input_section)
+ last_reloc = NULL;
+
+ last_input_section = sec;
+
+ /* Walk through the relocs looking for relaxing opportunities. */
+ irelend = internal_relocs + sec->reloc_count;
+ for (irel = internal_relocs; irel < irelend; irel++)
+ {
+ bfd_vma symval;
+
+ {
+ arelent bfd_reloc;
+
+ elf32_h8_info_to_howto (abfd, &bfd_reloc, irel);
+ }
+ /* Keep track of the previous reloc so that we can delete
+ some long jumps created by the compiler. */
+ if (irel != internal_relocs)
+ last_reloc = irel - 1;
+
+ switch(ELF32_R_TYPE (irel->r_info))
+ {
+ case R_H8_DIR24R8:
+ case R_H8_PCREL16:
+ case R_H8_DIR16A8:
+ case R_H8_DIR24A8:
+ case R_H8_DIR32A16:
+ case R_H8_DISP32A16:
+ break;
+ default:
+ continue;
+ }
+
+ /* Get the section contents if we haven't done so already. */
+ if (contents == NULL)
+ {
+ /* Get cached copy if it exists. */
+ if (elf_section_data (sec)->this_hdr.contents != NULL)
+ contents = elf_section_data (sec)->this_hdr.contents;
+ else
+ {
+ /* Go get them off disk. */
+ if (!bfd_malloc_and_get_section (abfd, sec, &contents))
+ goto error_return;
+ }
+ }
+
+ /* Read this BFD's local symbols if we haven't done so already. */
+ if (isymbuf == NULL && symtab_hdr->sh_info != 0)
+ {
+ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
+ if (isymbuf == NULL)
+ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
+ symtab_hdr->sh_info, 0,
+ NULL, NULL, NULL);
+ if (isymbuf == NULL)
+ goto error_return;
+ }
+
+ /* Get the value of the symbol referred to by the reloc. */
+ if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
+ {
+ /* A local symbol. */
+ Elf_Internal_Sym *isym;
+ asection *sym_sec;
+
+ isym = isymbuf + ELF32_R_SYM (irel->r_info);
+ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
+ symval = isym->st_value;
+ /* If the reloc is absolute, it will not have
+ a symbol or section associated with it. */
+ if (sym_sec)
+ symval += sym_sec->output_section->vma
+ + sym_sec->output_offset;
+ }
+ else
+ {
+ unsigned long indx;
+ struct elf_link_hash_entry *h;
+
+ /* An external symbol. */
+ indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
+ h = elf_sym_hashes (abfd)[indx];
+ BFD_ASSERT (h != NULL);
+ if (h->root.type != bfd_link_hash_defined
+ && h->root.type != bfd_link_hash_defweak)
+ {
+ /* This appears to be a reference to an undefined
+ symbol. Just ignore it--it will be caught by the
+ regular reloc processing. */
+ continue;
+ }
+
+ symval = (h->root.u.def.value
+ + h->root.u.def.section->output_section->vma
+ + h->root.u.def.section->output_offset);
+ }
+
+ /* For simplicity of coding, we are going to modify the section
+ contents, the section relocs, and the BFD symbol table. We
+ must tell the rest of the code not to free up this
+ information. It would be possible to instead create a table
+ of changes which have to be made, as is done in coff-mips.c;
+ that would be more work, but would require less memory when
+ the linker is run. */
+ switch (ELF32_R_TYPE (irel->r_info))
+ {
+ /* Try to turn a 24-bit absolute branch/call into an 8-bit
+ pc-relative branch/call. */
+ case R_H8_DIR24R8:
+ {
+ bfd_vma value = symval + irel->r_addend;
+ bfd_vma dot, gap;
+
+ /* Get the address of this instruction. */
+ dot = (sec->output_section->vma
+ + sec->output_offset + irel->r_offset - 1);
+
+ /* Compute the distance from this insn to the branch target. */
+ gap = value - dot;
+
+ /* If the distance is within -126..+130 inclusive, then we can
+ relax this jump. +130 is valid since the target will move
+ two bytes closer if we do relax this branch. */
+ if ((int) gap >= -126 && (int) gap <= 130)
+ {
+ unsigned char code;
+
+ /* Note that we've changed the relocs, section contents,
+ etc. */
+ elf_section_data (sec)->relocs = internal_relocs;
+ elf_section_data (sec)->this_hdr.contents = contents;
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+
+ /* Get the instruction code being relaxed. */
+ code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+
+ /* If the previous instruction conditionally jumped around
+ this instruction, we may be able to reverse the condition
+ and redirect the previous instruction to the target of
+ this instruction.
+
+ Such sequences are used by the compiler to deal with
+ long conditional branches.
+
+ Only perform this optimisation for jumps (code 0x5a) not
+ subroutine calls, as otherwise it could transform:
+
+ mov.w r0,r0
+ beq .L1
+ jsr @_bar
+ .L1: rts
+ _bar: rts
+ into:
+ mov.w r0,r0
+ bne _bar
+ rts
+ _bar: rts
+
+ which changes the call (jsr) into a branch (bne). */
+ if (code == 0x5a /* jmp24. */
+ && (int) gap <= 130
+ && (int) gap >= -128
+ && last_reloc
+ && ELF32_R_TYPE (last_reloc->r_info) == R_H8_PCREL8
+ && ELF32_R_SYM (last_reloc->r_info) < symtab_hdr->sh_info)
+ {
+ bfd_vma last_value;
+ asection *last_sym_sec;
+ Elf_Internal_Sym *last_sym;
+
+ /* We will need to examine the symbol used by the
+ previous relocation. */
+
+ last_sym = isymbuf + ELF32_R_SYM (last_reloc->r_info);
+ last_sym_sec
+ = bfd_section_from_elf_index (abfd, last_sym->st_shndx);
+ last_value = (last_sym->st_value
+ + last_sym_sec->output_section->vma
+ + last_sym_sec->output_offset);
+
+ /* Verify that the previous relocation was for a
+ branch around this instruction and that no symbol
+ exists at the current location. */
+ if (last_value == dot + 4
+ && last_reloc->r_offset + 2 == irel->r_offset
+ && ! elf32_h8_symbol_address_p (abfd, sec, dot))
+ {
+ /* We can eliminate this jump. Twiddle the
+ previous relocation as necessary. */
+ irel->r_info
+ = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
+ ELF32_R_TYPE (R_H8_NONE));
+
+ last_reloc->r_info
+ = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
+ ELF32_R_TYPE (R_H8_PCREL8));
+ last_reloc->r_addend = irel->r_addend;
+
+ code = bfd_get_8 (abfd,
+ contents + last_reloc->r_offset - 1);
+ code ^= 1;
+ bfd_put_8 (abfd,
+ code,
+ contents + last_reloc->r_offset - 1);
+
+ /* Delete four bytes of data. */
+ if (!elf32_h8_relax_delete_bytes (abfd, sec,
+ irel->r_offset - 1,
+ 4))
+ goto error_return;
+
+ *again = TRUE;
+ break;
+ }
+ }
+
+ if (code == 0x5e)
+ /* This is jsr24 */
+ bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 1); /* bsr8. */
+ else if (code == 0x5a)
+ /* This is jmp24 */
+ bfd_put_8 (abfd, 0x40, contents + irel->r_offset - 1); /* bra8. */
+ else
+ abort ();
+
+ /* Fix the relocation's type. */
+ irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
+ R_H8_PCREL8);
+
+ /* Delete two bytes of data. */
+ if (!elf32_h8_relax_delete_bytes (abfd, sec,
+ irel->r_offset + 1, 2))
+ goto error_return;
+
+ /* That will change things, so, we should relax again.
+ Note that this is not required, and it may be slow. */
+ *again = TRUE;
+ }
+ break;
+ }
+
+ /* Try to turn a 16-bit pc-relative branch into a 8-bit pc-relative
+ branch. */
+ case R_H8_PCREL16:
+ {
+ bfd_vma value = symval + irel->r_addend;
+ bfd_vma dot;
+ bfd_vma gap;
+
+ /* Get the address of this instruction. */
+ dot = (sec->output_section->vma
+ + sec->output_offset
+ + irel->r_offset - 2);
+
+ gap = value - dot;
+
+ /* If the distance is within -126..+130 inclusive, then we can
+ relax this jump. +130 is valid since the target will move
+ two bytes closer if we do relax this branch. */
+ if ((int) gap >= -126 && (int) gap <= 130)
+ {
+ unsigned char code;
+
+ /* Note that we've changed the relocs, section contents,
+ etc. */
+ elf_section_data (sec)->relocs = internal_relocs;
+ elf_section_data (sec)->this_hdr.contents = contents;
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+
+ /* Get the opcode. */
+ code = bfd_get_8 (abfd, contents + irel->r_offset - 2);
+
+ if (code == 0x58)
+ {
+ /* bCC:16 -> bCC:8 */
+ /* Get the second byte of the original insn, which
+ contains the condition code. */
+ code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+
+ /* Compute the first byte of the relaxed
+ instruction. The original sequence 0x58 0xX0
+ is relaxed to 0x4X, where X represents the
+ condition code. */
+ code &= 0xf0;
+ code >>= 4;
+ code |= 0x40;
+ bfd_put_8 (abfd, code, contents + irel->r_offset - 2); /* bCC:8. */
+ }
+ else if (code == 0x5c) /* bsr16. */
+ /* This is bsr. */
+ bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 2); /* bsr8. */
+ else
+ /* Might be MOVSD. */
+ break;
+
+ /* Fix the relocation's type. */
+ irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
+ R_H8_PCREL8);
+ irel->r_offset--;
+
+ /* Delete two bytes of data. */
+ if (!elf32_h8_relax_delete_bytes (abfd, sec,
+ irel->r_offset + 1, 2))
+ goto error_return;
+
+ /* That will change things, so, we should relax again.
+ Note that this is not required, and it may be slow. */
+ *again = TRUE;
+ }
+ break;
+ }
+
+ /* This is a 16-bit absolute address in one of the following
+ instructions:
+
+ "band", "bclr", "biand", "bild", "bior", "bist", "bixor",
+ "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and
+ "mov.b"
+
+ We may relax this into an 8-bit absolute address if it's in
+ the right range. */
+ case R_H8_DIR16A8:
+ {
+ bfd_vma value;
+
+ value = bfd_h8300_pad_address (abfd, symval + irel->r_addend);
+ if (value >= 0xffffff00u)
+ {
+ unsigned char code;
+ unsigned char temp_code;
+
+ /* Note that we've changed the relocs, section contents,
+ etc. */
+ elf_section_data (sec)->relocs = internal_relocs;
+ elf_section_data (sec)->this_hdr.contents = contents;
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+
+ /* Get the opcode. */
+ code = bfd_get_8 (abfd, contents + irel->r_offset - 2);
+
+ /* All instructions with R_H8_DIR16A8 start with
+ 0x6a. */
+ if (code != 0x6a)
+ abort ();
+
+ temp_code = code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+ /* If this is a mov.b instruction, clear the lower
+ nibble, which contains the source/destination
+ register number. */
+ if ((temp_code & 0x10) != 0x10)
+ temp_code &= 0xf0;
+
+ switch (temp_code)
+ {
+ case 0x00:
+ /* This is mov.b @aa:16,Rd. */
+ bfd_put_8 (abfd, (code & 0xf) | 0x20,
+ contents + irel->r_offset - 2);
+ break;
+ case 0x80:
+ /* This is mov.b Rs,@aa:16. */
+ bfd_put_8 (abfd, (code & 0xf) | 0x30,
+ contents + irel->r_offset - 2);
+ break;
+ case 0x18:
+ /* This is a bit-maniputation instruction that
+ stores one bit into memory, one of "bclr",
+ "bist", "bnot", "bset", and "bst". */
+ bfd_put_8 (abfd, 0x7f, contents + irel->r_offset - 2);
+ break;
+ case 0x10:
+ /* This is a bit-maniputation instruction that
+ loads one bit from memory, one of "band",
+ "biand", "bild", "bior", "bixor", "bld", "bor",
+ "btst", and "bxor". */
+ bfd_put_8 (abfd, 0x7e, contents + irel->r_offset - 2);
+ break;
+ default:
+ abort ();
+ }
+
+ /* Fix the relocation's type. */
+ irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
+ R_H8_DIR8);
+
+ /* Move the relocation. */
+ irel->r_offset--;
+
+ /* Delete two bytes of data. */
+ if (!elf32_h8_relax_delete_bytes (abfd, sec,
+ irel->r_offset + 1, 2))
+ goto error_return;
+
+ /* That will change things, so, we should relax again.
+ Note that this is not required, and it may be slow. */
+ *again = TRUE;
+ }
+ break;
+ }
+
+ /* This is a 24-bit absolute address in one of the following
+ instructions:
+
+ "band", "bclr", "biand", "bild", "bior", "bist", "bixor",
+ "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and
+ "mov.b"
+
+ We may relax this into an 8-bit absolute address if it's in
+ the right range. */
+ case R_H8_DIR24A8:
+ {
+ bfd_vma value;
+
+ value = bfd_h8300_pad_address (abfd, symval + irel->r_addend);
+ if (value >= 0xffffff00u)
+ {
+ unsigned char code;
+ unsigned char temp_code;
+
+ /* Note that we've changed the relocs, section contents,
+ etc. */
+ elf_section_data (sec)->relocs = internal_relocs;
+ elf_section_data (sec)->this_hdr.contents = contents;
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+
+ /* Get the opcode. */
+ code = bfd_get_8 (abfd, contents + irel->r_offset - 2);
+
+ /* All instructions with R_H8_DIR24A8 start with
+ 0x6a. */
+ if (code != 0x6a)
+ abort ();
+
+ temp_code = code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+
+ /* If this is a mov.b instruction, clear the lower
+ nibble, which contains the source/destination
+ register number. */
+ if ((temp_code & 0x30) != 0x30)
+ temp_code &= 0xf0;
+
+ switch (temp_code)
+ {
+ case 0x20:
+ /* This is mov.b @aa:24/32,Rd. */
+ bfd_put_8 (abfd, (code & 0xf) | 0x20,
+ contents + irel->r_offset - 2);
+ break;
+ case 0xa0:
+ /* This is mov.b Rs,@aa:24/32. */
+ bfd_put_8 (abfd, (code & 0xf) | 0x30,
+ contents + irel->r_offset - 2);
+ break;
+ case 0x38:
+ /* This is a bit-maniputation instruction that
+ stores one bit into memory, one of "bclr",
+ "bist", "bnot", "bset", and "bst". */
+ bfd_put_8 (abfd, 0x7f, contents + irel->r_offset - 2);
+ break;
+ case 0x30:
+ /* This is a bit-maniputation instruction that
+ loads one bit from memory, one of "band",
+ "biand", "bild", "bior", "bixor", "bld", "bor",
+ "btst", and "bxor". */
+ bfd_put_8 (abfd, 0x7e, contents + irel->r_offset - 2);
+ break;
+ default:
+ abort();
+ }
+
+ /* Fix the relocation's type. */
+ irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
+ R_H8_DIR8);
+ irel->r_offset--;
+
+ /* Delete four bytes of data. */
+ if (!elf32_h8_relax_delete_bytes (abfd, sec,
+ irel->r_offset + 1, 4))
+ goto error_return;
+
+ /* That will change things, so, we should relax again.
+ Note that this is not required, and it may be slow. */
+ *again = TRUE;
+ break;
+ }
+ }
+
+ /* Fall through. */
+
+ /* This is a 24-/32-bit absolute address in one of the
+ following instructions:
+
+ "band", "bclr", "biand", "bild", "bior", "bist",
+ "bixor", "bld", "bnot", "bor", "bset", "bst", "btst",
+ "bxor", "ldc.w", "stc.w" and "mov.[bwl]"
+
+ We may relax this into an 16-bit absolute address if it's
+ in the right range. */
+ case R_H8_DIR32A16:
+ {
+ bfd_vma value;
+
+ value = bfd_h8300_pad_address (abfd, symval + irel->r_addend);
+ if (value <= 0x7fff || value >= 0xffff8000u)
+ {
+ unsigned char code;
+ unsigned char op0, op1, op2, op3;
+ unsigned char *op_ptr;
+
+ /* Note that we've changed the relocs, section contents,
+ etc. */
+ elf_section_data (sec)->relocs = internal_relocs;
+ elf_section_data (sec)->this_hdr.contents = contents;
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+
+ if (irel->r_offset >= 4)
+ {
+ /* Check for 4-byte MOVA relaxation (SH-specific). */
+ int second_reloc = 0;
+
+ op_ptr = contents + irel->r_offset - 4;
+
+ if (last_reloc)
+ {
+ arelent bfd_reloc;
+ reloc_howto_type *h;
+ bfd_vma last_reloc_size;
+
+ elf32_h8_info_to_howto (abfd, &bfd_reloc, last_reloc);
+ h = bfd_reloc.howto;
+ last_reloc_size = 1 << h->size;
+ if (last_reloc->r_offset + last_reloc_size
+ == irel->r_offset)
+ {
+ op_ptr -= last_reloc_size;
+ second_reloc = 1;
+ }
+ }
+
+ if (irel + 1 < irelend)
+ {
+ Elf_Internal_Rela *next_reloc = irel + 1;
+ arelent bfd_reloc;
+ reloc_howto_type *h;
+ bfd_vma next_reloc_size;
+
+ elf32_h8_info_to_howto (abfd, &bfd_reloc, next_reloc);
+ h = bfd_reloc.howto;
+ next_reloc_size = 1 << h->size;
+ if (next_reloc->r_offset + next_reloc_size
+ == irel->r_offset)
+ {
+ op_ptr -= next_reloc_size;
+ second_reloc = 1;
+ }
+ }
+
+ op0 = bfd_get_8 (abfd, op_ptr + 0);
+ op1 = bfd_get_8 (abfd, op_ptr + 1);
+ op2 = bfd_get_8 (abfd, op_ptr + 2);
+ op3 = bfd_get_8 (abfd, op_ptr + 3);
+
+ if (op0 == 0x01
+ && (op1 & 0xdf) == 0x5f
+ && (op2 & 0x40) == 0x40
+ && (op3 & 0x80) == 0x80)
+ {
+ if ((op2 & 0x08) == 0)
+ second_reloc = 1;
+
+ if (second_reloc)
+ {
+ op3 &= ~0x08;
+ bfd_put_8 (abfd, op3, op_ptr + 3);
+ }
+ else
+ {
+ op2 &= ~0x08;
+ bfd_put_8 (abfd, op2, op_ptr + 2);
+ }
+ goto r_h8_dir32a16_common;
+ }
+ }
+
+ /* Now check for short version of MOVA. (SH-specific) */
+ op_ptr = contents + irel->r_offset - 2;
+ op0 = bfd_get_8 (abfd, op_ptr + 0);
+ op1 = bfd_get_8 (abfd, op_ptr + 1);
+
+ if (op0 == 0x7a
+ && (op1 & 0x88) == 0x80)
+ {
+ op1 |= 0x08;
+ bfd_put_8 (abfd, op1, op_ptr + 1);
+ goto r_h8_dir32a16_common;
+ }
+
+ /* Get the opcode. */
+ code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+
+ /* Fix the opcode. For all the instructions that
+ belong to this relaxation, we simply need to turn
+ off bit 0x20 in the previous byte. */
+ code &= ~0x20;
+
+ bfd_put_8 (abfd, code, contents + irel->r_offset - 1);
+
+ r_h8_dir32a16_common:
+ /* Fix the relocation's type. */
+ irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
+ R_H8_DIR16);
+
+ /* Delete two bytes of data. */
+ if (!elf32_h8_relax_delete_bytes (abfd, sec,
+ irel->r_offset + 1, 2))
+ goto error_return;
+
+ /* That will change things, so, we should relax again.
+ Note that this is not required, and it may be slow. */
+ *again = TRUE;
+ }
+ break; /* case R_H8_DIR32A16 */
+ }
+
+ case R_H8_DISP32A16:
+ /* mov.[bwl] @(displ:24/32+ERx) -> mov.[bwl] @(displ:16+ERx) 4 bytes
+ It is assured that instruction uses at least 4 bytes opcode before
+ reloc entry addressing mode "register indirect with displacement"
+ relaxing options (all saving 4 bytes):
+ 0x78 0sss0000 0x6A 0010dddd disp:32 mov.b @(d:32,ERs),Rd ->
+ 0x6E 0sssdddd disp:16 mov.b @(d:16,ERs),Rd
+ 0x78 0sss0000 0x6B 0010dddd disp:32 mov.w @(d:32,ERs),Rd ->
+ 0x6F 0sssdddd disp:16 mov.w @(d:16,ERs),Rd
+ 0x01 0x00 0x78 0sss0000 0x6B 00100ddd disp:32 mov.l @(d:32,ERs),ERd ->
+ 0x01 0x00 0x6F 0sss0ddd disp:16 mov.l @(d:16,ERs),ERd
+
+ 0x78 0ddd0000 0x6A 1010ssss disp:32 mov.b Rs,@(d:32,ERd) ->
+ 0x6E 1dddssss disp:16 mov.b Rs,@(d:16,ERd)
+ 0x78 0ddd0000 0x6B 1010ssss disp:32 mov.w Rs,@(d:32,ERd) ->
+ 0x6F 1dddssss disp:16 mov.w Rs,@(d:16,ERd)
+ 0x01 0x00 0x78 xddd0000 0x6B 10100sss disp:32 mov.l ERs,@(d:32,ERd) ->
+ 0x01 0x00 0x6F 1ddd0sss disp:16 mov.l ERs,@(d:16,ERd)
+ mov.l prefix 0x01 0x00 can be left as is and mov.l handled same
+ as mov.w/ */
+ {
+ bfd_vma value;
+
+ value = bfd_h8300_pad_address (abfd, symval + irel->r_addend);
+ if (value <= 0x7fff || value >= 0xffff8000u)
+ {
+ unsigned char op0, op1, op2, op3, op0n, op1n;
+ int relax = 0;
+
+ /* Note that we've changed the relocs, section contents,
+ etc. */
+ elf_section_data (sec)->relocs = internal_relocs;
+ elf_section_data (sec)->this_hdr.contents = contents;
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+
+ if (irel->r_offset >= 4)
+ {
+ op0 = bfd_get_8 (abfd, contents + irel->r_offset - 4);
+ op1 = bfd_get_8 (abfd, contents + irel->r_offset - 3);
+ op2 = bfd_get_8 (abfd, contents + irel->r_offset - 2);
+ op3 = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+
+ if (op0 == 0x78)
+ {
+ switch(op2)
+ {
+ case 0x6A:
+ if ((op1 & 0x8F) == 0x00 && (op3 & 0x70) == 0x20)
+ {
+ /* mov.b. */
+ op0n = 0x6E;
+ relax = 1;
+ }
+ break;
+ case 0x6B:
+ if ((op1 & 0x0F) == 0x00 && (op3 & 0x70) == 0x20)
+ {
+ /* mov.w/l. */
+ op0n = 0x6F;
+ relax = 1;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ if (relax)
+ {
+ op1n = (op3 & 0x8F) | (op1 & 0x70);
+ bfd_put_8 (abfd, op0n, contents + irel->r_offset - 4);
+ bfd_put_8 (abfd, op1n, contents + irel->r_offset - 3);
+
+ /* Fix the relocation's type. */
+ irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_H8_DIR16);
+ irel->r_offset -= 2;
+
+ /* Delete four bytes of data. */
+ if (!elf32_h8_relax_delete_bytes (abfd, sec, irel->r_offset + 2, 4))
+ goto error_return;
+
+ /* That will change things, so, we should relax again.
+ Note that this is not required, and it may be slow. */
+ *again = TRUE;
+ }
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (isymbuf != NULL
+ && symtab_hdr->contents != (unsigned char *) isymbuf)
+ {
+ if (! link_info->keep_memory)
+ free (isymbuf);
+ else
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+ }
+
+ if (contents != NULL
+ && elf_section_data (sec)->this_hdr.contents != contents)
+ {
+ if (! link_info->keep_memory)
+ free (contents);
+ else
+ {
+ /* Cache the section contents for elf_link_input_bfd. */
+ elf_section_data (sec)->this_hdr.contents = contents;
+ }