+ /* Convert GOT indices to actual offsets. */
+ g = mips_elf_got_offset_from_index (elf_hash_table (info)->dynobj,
+ abfd, g);
+ break;
+
+ case R_MIPS_HI16:
+ case R_MIPS_LO16:
+ case R_MIPS_GPREL16:
+ case R_MIPS_GPREL32:
+ case R_MIPS_LITERAL:
+ gp0 = _bfd_get_gp_value (input_bfd);
+ gp = _bfd_get_gp_value (abfd);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Figure out what kind of relocation is being performed. */
+ switch (r_type)
+ {
+ case R_MIPS_NONE:
+ return bfd_reloc_continue;
+
+ case R_MIPS_16:
+ value = symbol + mips_elf_sign_extend (addend, 16);
+ overflowed_p = mips_elf_overflow_p (value, 16);
+ break;
+
+ case R_MIPS_32:
+ case R_MIPS_REL32:
+ case R_MIPS_64:
+ if ((info->shared
+ || (elf_hash_table (info)->dynamic_sections_created
+ && h != NULL
+ && ((h->root.elf_link_hash_flags & ELF_LINK_HASH_DEF_REGULAR)
+ == 0)))
+ && (input_section->flags & SEC_ALLOC) != 0)
+ {
+ /* If we're creating a shared library, or this relocation is
+ against a symbol in a shared library, then we can't know
+ where the symbol will end up. So, we create a relocation
+ record in the output, and leave the job up to the dynamic
+ linker. */
+ value = addend;
+ if (!mips_elf_create_dynamic_relocation (abfd,
+ info,
+ relocation,
+ h,
+ sec,
+ symbol,
+ &value,
+ input_section))
+ return false;
+ }
+ else
+ {
+ if (r_type != R_MIPS_REL32)
+ value = symbol + addend;
+ else
+ value = addend;
+ }
+ value &= howto->dst_mask;
+ break;
+
+ case R_MIPS_PC32:
+ case R_MIPS_PC64:
+ case R_MIPS_GNU_REL_LO16:
+ value = symbol + addend - p;
+ value &= howto->dst_mask;
+ break;
+
+ case R_MIPS_GNU_REL16_S2:
+ value = symbol + mips_elf_sign_extend (addend << 2, 18) - p;
+ overflowed_p = mips_elf_overflow_p (value, 18);
+ value = (value >> 2) & howto->dst_mask;
+ break;
+
+ case R_MIPS_GNU_REL_HI16:
+ value = mips_elf_high (addend + symbol - p);
+ value &= howto->dst_mask;
+ break;
+
+ case R_MIPS16_26:
+ /* The calculation for R_MIPS_26 is just the same as for an
+ R_MIPS_26. It's only the storage of the relocated field into
+ the output file that's different. That's handled in
+ mips_elf_perform_relocation. So, we just fall through to the
+ R_MIPS_26 case here. */
+ case R_MIPS_26:
+ if (local_p)
+ value = (((addend << 2) | (p & 0xf0000000)) + symbol) >> 2;
+ else
+ value = (mips_elf_sign_extend (addend << 2, 28) + symbol) >> 2;
+ value &= howto->dst_mask;
+ break;
+
+ case R_MIPS_HI16:
+ if (!gp_disp_p)
+ {
+ value = mips_elf_high (addend + symbol);
+ value &= howto->dst_mask;
+ }
+ else
+ {
+ value = mips_elf_high (addend + gp - p);
+ overflowed_p = mips_elf_overflow_p (value, 16);
+ }
+ break;
+
+ case R_MIPS_LO16:
+ if (!gp_disp_p)
+ value = (symbol + addend) & howto->dst_mask;
+ else
+ {
+ value = addend + gp - p + 4;
+ /* The MIPS ABI requires checking the R_MIPS_LO16 relocation
+ for overflow. But, on, say, Irix 5, relocations against
+ _gp_disp are normally generated from the .cpload
+ pseudo-op. It generates code that normally looks like
+ this:
+
+ lui $gp,%hi(_gp_disp)
+ addiu $gp,$gp,%lo(_gp_disp)
+ addu $gp,$gp,$t9
+
+ Here $t9 holds the address of the function being called,
+ as required by the MIPS ELF ABI. The R_MIPS_LO16
+ relocation can easily overflow in this situation, but the
+ R_MIPS_HI16 relocation will handle the overflow.
+ Therefore, we consider this a bug in the MIPS ABI, and do
+ not check for overflow here. */
+ }
+ break;
+
+ case R_MIPS_LITERAL:
+ /* Because we don't merge literal sections, we can handle this
+ just like R_MIPS_GPREL16. In the long run, we should merge
+ shared literals, and then we will need to additional work
+ here. */
+
+ /* Fall through. */
+
+ case R_MIPS16_GPREL:
+ /* The R_MIPS16_GPREL performs the same calculation as
+ R_MIPS_GPREL16, but stores the relocated bits in a different
+ order. We don't need to do anything special here; the
+ differences are handled in mips_elf_perform_relocation. */
+ case R_MIPS_GPREL16:
+ if (local_p)
+ value = mips_elf_sign_extend (addend, 16) + symbol + gp0 - gp;
+ else
+ value = mips_elf_sign_extend (addend, 16) + symbol - gp;
+ overflowed_p = mips_elf_overflow_p (value, 16);
+ break;
+
+ case R_MIPS_GOT16:
+ if (local_p)
+ {
+ value = mips_elf_got16_entry (abfd, info, symbol + addend);
+ if (value == (bfd_vma) -1)
+ return false;
+ value
+ = mips_elf_got_offset_from_index (elf_hash_table (info)->dynobj,
+ abfd,
+ value);
+ overflowed_p = mips_elf_overflow_p (value, 16);
+ break;
+ }
+
+ /* Fall through. */
+
+ case R_MIPS_CALL16:
+ case R_MIPS_GOT_DISP:
+ value = g;
+ overflowed_p = mips_elf_overflow_p (value, 16);
+ break;
+
+ case R_MIPS_GPREL32:
+ value = (addend + symbol + gp0 - gp) & howto->dst_mask;
+ break;
+
+ case R_MIPS_PC16:
+ value = mips_elf_sign_extend (addend, 16) + symbol - p;
+ value = (bfd_vma) ((bfd_signed_vma) value / 4);
+ overflowed_p = mips_elf_overflow_p (value, 16);
+ break;
+
+ case R_MIPS_GOT_HI16:
+ case R_MIPS_CALL_HI16:
+ /* We're allowed to handle these two relocations identically.
+ The dynamic linker is allowed to handle the CALL relocations
+ differently by creating a lazy evaluation stub. */
+ value = g;
+ value = mips_elf_high (value);
+ value &= howto->dst_mask;
+ break;
+
+ case R_MIPS_GOT_LO16:
+ case R_MIPS_CALL_LO16:
+ value = g & howto->dst_mask;
+ break;
+
+ case R_MIPS_GOT_PAGE:
+ value = mips_elf_got_page (abfd, info, symbol + addend, NULL);
+ if (value == (bfd_vma) -1)
+ return false;
+ value = mips_elf_got_offset_from_index (elf_hash_table (info)->dynobj,
+ abfd,
+ value);
+ overflowed_p = mips_elf_overflow_p (value, 16);
+ break;
+
+ case R_MIPS_GOT_OFST:
+ mips_elf_got_page (abfd, info, symbol + addend, &value);
+ overflowed_p = mips_elf_overflow_p (value, 16);
+ break;
+
+ case R_MIPS_SUB:
+ value = symbol - addend;
+ value &= howto->dst_mask;
+ break;
+
+ case R_MIPS_HIGHER:
+ value = mips_elf_higher (addend + symbol);
+ value &= howto->dst_mask;
+ break;
+
+ case R_MIPS_HIGHEST:
+ value = mips_elf_highest (addend + symbol);
+ value &= howto->dst_mask;
+ break;
+
+ case R_MIPS_SCN_DISP:
+ value = symbol + addend - sec->output_offset;
+ value &= howto->dst_mask;
+ break;
+
+ case R_MIPS_PJUMP:
+ case R_MIPS_JALR:
+ /* Both of these may be ignored. R_MIPS_JALR is an optimization
+ hint; we could improve performance by honoring that hint. */
+ return bfd_reloc_continue;
+
+ case R_MIPS_GNU_VTINHERIT:
+ case R_MIPS_GNU_VTENTRY:
+ /* We don't do anything with these at present. */
+ return bfd_reloc_continue;
+
+ default:
+ /* An unrecognized relocation type. */
+ return bfd_reloc_notsupported;
+ }
+
+ /* Store the VALUE for our caller. */
+ *valuep = value;
+ return overflowed_p ? bfd_reloc_overflow : bfd_reloc_ok;
+}
+
+/* Obtain the field relocated by RELOCATION. */
+
+static bfd_vma
+mips_elf_obtain_contents (howto, relocation, input_bfd, contents)
+ reloc_howto_type *howto;
+ const Elf_Internal_Rela *relocation;
+ bfd *input_bfd;
+ bfd_byte *contents;
+{
+ bfd_vma x;
+ bfd_byte *location = contents + relocation->r_offset;
+
+ /* Obtain the bytes. */
+ x = bfd_get (8 * bfd_get_reloc_size (howto), input_bfd, location);
+
+ if ((ELF32_R_TYPE (relocation->r_info) == R_MIPS16_26
+ || ELF32_R_TYPE (relocation->r_info) == R_MIPS16_GPREL)
+ && bfd_little_endian (input_bfd))
+ /* The two 16-bit words will be reversed on a little-endian
+ system. See mips_elf_perform_relocation for more details. */
+ x = (((x & 0xffff) << 16) | ((x & 0xffff0000) >> 16));
+
+ return x;
+}
+
+/* It has been determined that the result of the RELOCATION is the
+ VALUE. Use HOWTO to place VALUE into the output file at the
+ appropriate position. The SECTION is the section to which the
+ relocation applies. If REQUIRE_JALX is true, then the opcode used
+ for the relocation must be either JAL or JALX, and it is
+ unconditionally converted to JALX.
+
+ Returns false if anything goes wrong. */
+
+static boolean
+mips_elf_perform_relocation (info, howto, relocation, value,
+ input_bfd, input_section,
+ contents, require_jalx)
+ struct bfd_link_info *info;
+ reloc_howto_type *howto;
+ const Elf_Internal_Rela *relocation;
+ bfd_vma value;
+ bfd *input_bfd;
+ asection *input_section;
+ bfd_byte *contents;
+ boolean require_jalx;
+{
+ bfd_vma x;
+ bfd_byte *location;
+ int r_type = ELF32_R_TYPE (relocation->r_info);
+
+ /* Figure out where the relocation is occurring. */
+ location = contents + relocation->r_offset;
+
+ /* Obtain the current value. */
+ x = mips_elf_obtain_contents (howto, relocation, input_bfd, contents);
+
+ /* Clear the field we are setting. */
+ x &= ~howto->dst_mask;
+
+ /* If this is the R_MIPS16_26 relocation, we must store the
+ value in a funny way. */
+ if (r_type == R_MIPS16_26)
+ {
+ /* R_MIPS16_26 is used for the mips16 jal and jalx instructions.
+ Most mips16 instructions are 16 bits, but these instructions
+ are 32 bits.
+
+ The format of these instructions is:
+
+ +--------------+--------------------------------+
+ ! JALX ! X! Imm 20:16 ! Imm 25:21 !
+ +--------------+--------------------------------+
+ ! Immediate 15:0 !
+ +-----------------------------------------------+
+
+ JALX is the 5-bit value 00011. X is 0 for jal, 1 for jalx.
+ Note that the immediate value in the first word is swapped.
+
+ When producing a relocateable object file, R_MIPS16_26 is
+ handled mostly like R_MIPS_26. In particular, the addend is
+ stored as a straight 26-bit value in a 32-bit instruction.
+ (gas makes life simpler for itself by never adjusting a
+ R_MIPS16_26 reloc to be against a section, so the addend is
+ always zero). However, the 32 bit instruction is stored as 2
+ 16-bit values, rather than a single 32-bit value. In a
+ big-endian file, the result is the same; in a little-endian
+ file, the two 16-bit halves of the 32 bit value are swapped.
+ This is so that a disassembler can recognize the jal
+ instruction.
+
+ When doing a final link, R_MIPS16_26 is treated as a 32 bit
+ instruction stored as two 16-bit values. The addend A is the
+ contents of the targ26 field. The calculation is the same as
+ R_MIPS_26. When storing the calculated value, reorder the
+ immediate value as shown above, and don't forget to store the
+ value as two 16-bit values.
+
+ To put it in MIPS ABI terms, the relocation field is T-targ26-16,
+ defined as
+
+ big-endian:
+ +--------+----------------------+
+ | | |
+ | | targ26-16 |
+ |31 26|25 0|
+ +--------+----------------------+
+
+ little-endian:
+ +----------+------+-------------+
+ | | | |
+ | sub1 | | sub2 |
+ |0 9|10 15|16 31|
+ +----------+--------------------+
+ where targ26-16 is sub1 followed by sub2 (i.e., the addend field A is
+ ((sub1 << 16) | sub2)).
+
+ When producing a relocateable object file, the calculation is
+ (((A < 2) | (P & 0xf0000000) + S) >> 2)
+ When producing a fully linked file, the calculation is
+ let R = (((A < 2) | (P & 0xf0000000) + S) >> 2)
+ ((R & 0x1f0000) << 5) | ((R & 0x3e00000) >> 5) | (R & 0xffff) */
+
+ if (!info->relocateable)
+ /* Shuffle the bits according to the formula above. */
+ value = (((value & 0x1f0000) << 5)
+ | ((value & 0x3e00000) >> 5)
+ | (value & 0xffff));
+
+ }
+ else if (r_type == R_MIPS16_GPREL)
+ {
+ /* R_MIPS16_GPREL is used for GP-relative addressing in mips16
+ mode. A typical instruction will have a format like this:
+
+ +--------------+--------------------------------+
+ ! EXTEND ! Imm 10:5 ! Imm 15:11 !
+ +--------------+--------------------------------+
+ ! Major ! rx ! ry ! Imm 4:0 !
+ +--------------+--------------------------------+
+
+ EXTEND is the five bit value 11110. Major is the instruction
+ opcode.
+
+ This is handled exactly like R_MIPS_GPREL16, except that the
+ addend is retrieved and stored as shown in this diagram; that
+ is, the Imm fields above replace the V-rel16 field.
+
+ All we need to do here is shuffle the bits appropriately. As
+ above, the two 16-bit halves must be swapped on a
+ little-endian system. */
+ value = (((value & 0x7e0) << 16)
+ | ((value & 0xf800) << 5)
+ | (value & 0x1f));
+ }
+
+ /* Set the field. */
+ x |= (value & howto->dst_mask);
+
+ /* If required, turn JAL into JALX. */
+ if (require_jalx)
+ {
+ boolean ok;
+ bfd_vma opcode = x >> 26;
+ bfd_vma jalx_opcode;
+
+ /* Check to see if the opcode is already JAL or JALX. */
+ if (r_type == R_MIPS16_26)