+bfd_boolean
+spu_elf_size_sections (bfd * output_bfd, struct bfd_link_info *info)
+{
+ struct spu_link_hash_table *htab = spu_hash_table (info);
+ if (htab->params->emit_fixups)
+ {
+ asection *sfixup = htab->sfixup;
+ int fixup_count = 0;
+ bfd *ibfd;
+ size_t size;
+
+ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next)
+ {
+ asection *isec;
+
+ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour)
+ continue;
+
+ /* Walk over each section attached to the input bfd. */
+ for (isec = ibfd->sections; isec != NULL; isec = isec->next)
+ {
+ Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
+ bfd_vma base_end;
+
+ /* If there aren't any relocs, then there's nothing more
+ to do. */
+ if ((isec->flags & SEC_ALLOC) == 0
+ || (isec->flags & SEC_RELOC) == 0
+ || isec->reloc_count == 0)
+ continue;
+
+ /* Get the relocs. */
+ internal_relocs =
+ _bfd_elf_link_read_relocs (ibfd, isec, NULL, NULL,
+ info->keep_memory);
+ if (internal_relocs == NULL)
+ return FALSE;
+
+ /* 1 quadword can contain up to 4 R_SPU_ADDR32
+ relocations. They are stored in a single word by
+ saving the upper 28 bits of the address and setting the
+ lower 4 bits to a bit mask of the words that have the
+ relocation. BASE_END keeps track of the next quadword. */
+ irela = internal_relocs;
+ irelaend = irela + isec->reloc_count;
+ base_end = 0;
+ for (; irela < irelaend; irela++)
+ if (ELF32_R_TYPE (irela->r_info) == R_SPU_ADDR32
+ && irela->r_offset >= base_end)
+ {
+ base_end = (irela->r_offset & ~(bfd_vma) 15) + 16;
+ fixup_count++;
+ }
+ }
+ }
+
+ /* We always have a NULL fixup as a sentinel */
+ size = (fixup_count + 1) * FIXUP_RECORD_SIZE;
+ if (!bfd_set_section_size (output_bfd, sfixup, size))
+ return FALSE;
+ sfixup->contents = (bfd_byte *) bfd_zalloc (info->input_bfds, size);
+ if (sfixup->contents == NULL)
+ return FALSE;
+ }
+ return TRUE;
+}
+