+ else if (bfd_little_endian (abfd))
+ {
+ /* If the input byte stream contains:
+ 05 04 03 02 01 00
+ and VerilogDataWidth is 4 then we want to emit:
+ 02030405 0001 */
+ int i;
+
+ for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
+ {
+ for (i = VerilogDataWidth - 1; i >= 0; i--)
+ {
+ TOHEX (dst, src[i]);
+ dst += 2;
+ }
+ *dst++ = ' ';
+ }
+
+ /* Emit any remaining bytes. Be careful not to read beyond "end". */
+ while (end > src)
+ {
+ -- end;
+ TOHEX (dst, *end);
+ dst += 2;
+ }
+ }
+ else
+ {
+ for (src = data; src < end;)
+ {
+ TOHEX (dst, *src);
+ dst += 2;
+ ++ src;
+ if ((src - data) % VerilogDataWidth == 0)
+ *dst++ = ' ';
+ }
+ }
+