[AArch64] Add ARMv8.3 javascript floating-point conversion instruction

[deliverable/binutils-gdb.git] / cpu / frv.opc

diff --git a/cpu/frv.opc b/cpu/frv.opc
index 5d2dc896039a74486a7469e5b21d91d3cadd89c4..869155d67afc1294f5516fb9d9ff955474c72cc2 100644 (file)
--- a/cpu/frv.opc
+++ b/cpu/frv.opc
@@ -1,6 +1,7 @@
 /* Fujitsu FRV opcode support, for GNU Binutils.  -*- C -*-
 
 /* Fujitsu FRV opcode support, for GNU Binutils.  -*- C -*-
 

-   Copyright 2000, 2001, 2003, 2004, 2005 Free Software Foundation, Inc.
+   Copyright 2000, 2001, 2003, 2004, 2005, 2007, 2009
+   Free Software Foundation, Inc.

 
    Contributed by Red Hat Inc; developed under contract from Fujitsu.
 
 
    Contributed by Red Hat Inc; developed under contract from Fujitsu.
 


@@ -8,7 +9,7 @@
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by

-   the Free Software Foundation; either version 2 of the License, or
+   the Free Software Foundation; either version 3 of the License, or

    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,


@@ -21,6 +22,7 @@
    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 

+

 /* This file is an addendum to frv.cpu.  Heavy use of C code isn't
    appropriate in .cpu files, so it resides here.  This especially applies
    to assembly/disassembly where parsing/printing can be quite involved.
 /* This file is an addendum to frv.cpu.  Heavy use of C code isn't
    appropriate in .cpu files, so it resides here.  This especially applies
    to assembly/disassembly where parsing/printing can be quite involved.


@@ -79,6 +81,9 @@ int spr_valid           (long);
 #include "elf/frv.h"
 #include <stdio.h>
 
 #include "elf/frv.h"
 #include <stdio.h>
 

+/* DEBUG appears below as argument of OP macro.  */
+#undef DEBUG
+

 /* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV
    development tree.  */
 
 /* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV
    development tree.  */
 


@@ -840,7 +845,7 @@ check_insn_major_constraints (FRV_VLIW *vliw,
 int
 frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
 {
 int
 frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
 {

-  int index;
+  int slot_index;

   CGEN_ATTR_VALUE_ENUM_TYPE major;
   CGEN_ATTR_VALUE_ENUM_TYPE unit;
   VLIW_COMBO *new_vliw;
   CGEN_ATTR_VALUE_ENUM_TYPE major;
   CGEN_ATTR_VALUE_ENUM_TYPE unit;
   VLIW_COMBO *new_vliw;


@@ -848,8 +853,8 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
   if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn))
     return 1;
 
   if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn))
     return 1;
 

-  index = vliw->next_slot;
-  if (index >= FRV_VLIW_SIZE)
+  slot_index = vliw->next_slot;
+  if (slot_index >= FRV_VLIW_SIZE)

     return 1;
 
   unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT);
     return 1;
 
   unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT);


@@ -876,7 +881,7 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
       break;
     }
 
       break;
     }
 

-  if (index <= 0)
+  if (slot_index <= 0)

     {
       /* Any insn can be added to slot 0.  */
       while (! match_unit (vliw, unit, (*vliw->current_vliw)[0]))
     {
       /* Any insn can be added to slot 0.  */
       while (! match_unit (vliw, unit, (*vliw->current_vliw)[0]))


@@ -896,8 +901,8 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
       if (new_vliw && check_insn_major_constraints (vliw, major, insn))
        {
          vliw->current_vliw = new_vliw;
       if (new_vliw && check_insn_major_constraints (vliw, major, insn))
        {
          vliw->current_vliw = new_vliw;

-         vliw->major[index] = major;
-         vliw->insn[index] = insn;
+         vliw->major[slot_index] = major;
+         vliw->insn[slot_index] = insn;

          vliw->next_slot++;
          return 0;
        }
          vliw->next_slot++;
          return 0;
        }


@@ -1338,11 +1343,11 @@ parse_uhi16 (CGEN_CPU_DESC cd,
          if (errmsg == NULL
              && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
            {
          if (errmsg == NULL
              && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
            {

-             /* If bfd_vma is wider than 32 bits, but we have a sign-
-                or zero-extension, truncate it.  */
-             if (value >= - ((bfd_vma)1 << 31)
-                 || value <= ((bfd_vma)1 << 31) - (bfd_vma)1)
-               value &= (((bfd_vma)1 << 16) << 16) - 1;
+             /* If value is wider than 32 bits then be
+                careful about how we extract bits 16-31.  */
+             if (sizeof (value) > 4)
+               value &= (((bfd_vma)1 << 16) << 16) - 1;
+

              value >>= 16;
            }
          *valuep = value;
              value >>= 16;
            }
          *valuep = value;