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RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.
[deliverable/binutils-gdb.git]
/
cpu
/
lm32.cpu
diff --git
a/cpu/lm32.cpu
b/cpu/lm32.cpu
index 31b943d79eba79fde1d9e1235ed00cc6dbb16add..83c839f3392f857bca6f062ef07413a0ac594b31 100644
(file)
--- a/
cpu/lm32.cpu
+++ b/
cpu/lm32.cpu
@@
-1,5
+1,5
@@
; Lattice Mico32 CPU description. -*- Scheme -*-
; Lattice Mico32 CPU description. -*- Scheme -*-
-; Copyright 2008
, 2009
Free Software Foundation, Inc.
+; Copyright 2008
-2013
Free Software Foundation, Inc.
; Contributed by Jon Beniston <jon@beniston.com>
;
; This file is part of the GNU Binutils.
; Contributed by Jon Beniston <jon@beniston.com>
;
; This file is part of the GNU Binutils.
@@
-101,9
+101,11
@@
(EBA 7)
(DC 8)
(DEBA 9)
(EBA 7)
(DC 8)
(DEBA 9)
+ (CFG2 10)
(JTX 14) (JRX 15)
(BP0 16) (BP1 17) (BP2 18) (BP3 19)
(WP0 24) (WP1 25) (WP2 26) (WP3 27)
(JTX 14) (JRX 15)
(BP0 16) (BP1 17) (BP2 18) (BP3 19)
(WP0 24) (WP1 25) (WP2 26) (WP3 27)
+ (PSW 29) (TLBVADDR 30) (TLBPADDR 31) (TLBBADVADDR 31)
)
)
() ()
)
)
() ()
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