Add support for .MIPS.options section.

[deliverable/binutils-gdb.git] / cpu / mt.opc

diff --git a/cpu/mt.opc b/cpu/mt.opc
index e3b32db7b94b5beb5064831ae9a1c5ee12d63878..d988cc25e9085e800c81d8ca59a38e42c62c9740 100644 (file)
--- a/cpu/mt.opc
+++ b/cpu/mt.opc
@@ -1,5 +1,5 @@
 /* Morpho Technologies mRISC opcode support, for GNU Binutils.  -*- C -*-
 /* Morpho Technologies mRISC opcode support, for GNU Binutils.  -*- C -*-

-   Copyright 2001 Free Software Foundation, Inc.
+   Copyright 2001, 2007, 2008, 2009, 2012 Free Software Foundation, Inc.

 
    Contributed by Red Hat Inc; developed under contract from
    Morpho Technologies.
 
    Contributed by Red Hat Inc; developed under contract from
    Morpho Technologies.


@@ -8,7 +8,7 @@
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by

-   the Free Software Foundation; either version 2 of the License, or
+   the Free Software Foundation; either version 3 of the License, or

    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,


@@ -18,19 +18,17 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software

-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */

 
 

-*/

 
 

-/*
-   Each section is delimited with start and end markers.
+/* Each section is delimited with start and end markers.

 
    <arch>-opc.h additions use: "-- opc.h"
    <arch>-opc.c additions use: "-- opc.c"
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
 
    <arch>-opc.h additions use: "-- opc.h"
    <arch>-opc.c additions use: "-- opc.c"
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"

-   <arch>-ibd.h additions use: "-- ibd.h"
-*/
+   <arch>-ibd.h additions use: "-- ibd.h"  */

 \f
 /* -- opc.h */
 
 \f
 /* -- opc.h */
 


@@ -46,11 +44,11 @@
 #define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
 
 #define CGEN_ASM_HASH_SIZE 127
 #define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
 
 #define CGEN_ASM_HASH_SIZE 127

-#define CGEN_ASM_HASH(insn) ms1_asm_hash (insn)
+#define CGEN_ASM_HASH(insn) mt_asm_hash (insn)

 
 

-extern unsigned int ms1_asm_hash (const char *);
+extern unsigned int mt_asm_hash (const char *);

 
 

-extern int ms1_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+extern int mt_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);

 
 \f
 /* -- opc.c */
 
 \f
 /* -- opc.c */


@@ -59,8 +57,7 @@ extern int ms1_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
 /* Special check to ensure that instruction exists for given machine.  */
 
 int
 /* Special check to ensure that instruction exists for given machine.  */
 
 int

-ms1_cgen_insn_supported (CGEN_CPU_DESC cd,
-                        const CGEN_INSN *insn)
+mt_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)

 {
   int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
 
 {
   int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
 


@@ -74,7 +71,7 @@ ms1_cgen_insn_supported (CGEN_CPU_DESC cd,
 /* A better hash function for instruction mnemonics.  */
 
 unsigned int
 /* A better hash function for instruction mnemonics.  */
 
 unsigned int

-ms1_asm_hash (const char* insn)
+mt_asm_hash (const char* insn)

 {
   unsigned int hash;
   const char* m = insn;
 {
   unsigned int hash;
   const char* m = insn;


@@ -113,9 +110,9 @@ parse_loopsize (CGEN_CPU_DESC cd,
   bfd_vma value;
 
   /* Is it a control transfer instructions?  */ 
   bfd_vma value;
 
   /* Is it a control transfer instructions?  */ 

-  if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_LOOPSIZE)
+  if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_LOOPSIZE)

     {
     {

-      code = BFD_RELOC_MS1_PCINSN8;
+      code = BFD_RELOC_MT_PCINSN8;

       errmsg = cgen_parse_address (cd, strp, opindex, code,
                                    & result_type, & value);
       *valuep = value;
       errmsg = cgen_parse_address (cd, strp, opindex, code,
                                    & result_type, & value);
       *valuep = value;


@@ -138,7 +135,7 @@ parse_imm16 (CGEN_CPU_DESC cd,
   bfd_vma value;
 
   /* Is it a control transfer instructions?  */ 
   bfd_vma value;
 
   /* Is it a control transfer instructions?  */ 

-  if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16O)
+  if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16O)

     {
       code = BFD_RELOC_16_PCREL;
       errmsg = cgen_parse_address (cd, strp, opindex, code,
     {
       code = BFD_RELOC_16_PCREL;
       errmsg = cgen_parse_address (cd, strp, opindex, code,


@@ -154,7 +151,7 @@ parse_imm16 (CGEN_CPU_DESC cd,
 
   /* If it's not a control transfer instruction, then
      we have to check for %OP relocating operators.  */
 
   /* If it's not a control transfer instruction, then
      we have to check for %OP relocating operators.  */

-  if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16L)
+  if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16L)

     ;
   else if (strncmp (*strp, "%hi16", 5) == 0)
     {
     ;
   else if (strncmp (*strp, "%hi16", 5) == 0)
     {


@@ -193,7 +190,7 @@ parse_imm16 (CGEN_CPU_DESC cd,
               break;
 
             default:
               break;
 
             default:

-              errmsg = _("%operator operand is not a symbol");
+              errmsg = _("The percent-operator's operand is not a symbol");

               break;
              }
         }
               break;
              }
         }


@@ -203,7 +200,7 @@ parse_imm16 (CGEN_CPU_DESC cd,
     {
       /* Parse hex values like 0xffff as unsigned, and sign extend
         them manually.  */
     {
       /* Parse hex values like 0xffff as unsigned, and sign extend
         them manually.  */

-      int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MS1_OPERAND_IMM16);
+      int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MT_OPERAND_IMM16);

 
       if ((*strp)[0] == '0'
          && ((*strp)[1] == 'x' || (*strp)[1] == 'X'))
 
       if ((*strp)[0] == '0'
          && ((*strp)[1] == 'x' || (*strp)[1] == 'X'))


@@ -235,10 +232,10 @@ parse_imm16 (CGEN_CPU_DESC cd,
        }
       else  
        {
        }
       else  
        {

-          /* MS1_OPERAND_IMM16Z.  Parse as an unsigned integer.  */
+          /* MT_OPERAND_IMM16Z.  Parse as an unsigned integer.  */

           errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep);
 
           errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep);
 

-         if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16
+         if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16

              && *valuep >= 0x8000
              && *valuep <= 0xffff)
            *valuep -= 0x10000;
              && *valuep >= 0x8000
              && *valuep <= 0xffff)
            *valuep -= 0x10000;


@@ -450,7 +447,7 @@ print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 

-  info->fprintf_func (info->stream, "$%lx", value);
+  info->fprintf_func (info->stream, "$%lx", value & 0xffffffff);

 
   if (0)
     print_normal (cd, dis_info, value, attrs, pc, length);
 
   if (0)
     print_normal (cd, dis_info, value, attrs, pc, length);