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e1000e: Fix HW Error on es2lan, ARP capture issue by BMC
[deliverable/linux.git]
/
drivers
/
net
/
e1000e
/
phy.c
diff --git
a/drivers/net/e1000e/phy.c
b/drivers/net/e1000e/phy.c
index 793231810ae0a6c119aef80111c2d428578812ca..e102332a6beed4e49588f2c37063a0429fef85f8 100644
(file)
--- a/
drivers/net/e1000e/phy.c
+++ b/
drivers/net/e1000e/phy.c
@@
-1,7
+1,7
@@
/*******************************************************************************
Intel PRO/1000 Linux driver
/*******************************************************************************
Intel PRO/1000 Linux driver
- Copyright(c) 1999 - 200
7
Intel Corporation.
+ Copyright(c) 1999 - 200
8
Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
@@
-49,8
+49,7
@@
static const u16 e1000_igp_2_cable_length_table[] =
100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
124};
#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
124};
#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
- (sizeof(e1000_igp_2_cable_length_table) / \
- sizeof(e1000_igp_2_cable_length_table[0]))
+ ARRAY_SIZE(e1000_igp_2_cable_length_table)
/**
* e1000e_check_reset_block_generic - Check if PHY reset is blocked
/**
* e1000e_check_reset_block_generic - Check if PHY reset is blocked
@@
-117,15
+116,15
@@
s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
}
/**
}
/**
- * e1000_read_phy_reg_mdic - Read MDI control register
+ * e1000
e
_read_phy_reg_mdic - Read MDI control register
* @hw: pointer to the HW structure
* @offset: register offset to be read
* @data: pointer to the read data
*
* @hw: pointer to the HW structure
* @offset: register offset to be read
* @data: pointer to the read data
*
- * Reads the MDI control reg
si
ter in the PHY at offset and stores the
+ * Reads the MDI control reg
is
ter in the PHY at offset and stores the
* information read to data.
**/
* information read to data.
**/
-s
tatic s32 e1000
_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
+s
32 e1000e
_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
{
struct e1000_phy_info *phy = &hw->phy;
u32 i, mdic = 0;
{
struct e1000_phy_info *phy = &hw->phy;
u32 i, mdic = 0;
@@
-135,7
+134,8
@@
static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
return -E1000_ERR_PARAM;
}
return -E1000_ERR_PARAM;
}
- /* Set up Op-code, Phy Address, and register offset in the MDI
+ /*
+ * Set up Op-code, Phy Address, and register offset in the MDI
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
@@
-145,8
+145,12
@@
static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
ew32(MDIC, mdic);
ew32(MDIC, mdic);
- /* Poll the ready bit to see if the MDI read completed */
- for (i = 0; i < 64; i++) {
+ /*
+ * Poll the ready bit to see if the MDI read completed
+ * Increasing the time out as testing showed failures with
+ * the lower time out
+ */
+ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
udelay(50);
mdic = er32(MDIC);
if (mdic & E1000_MDIC_READY)
udelay(50);
mdic = er32(MDIC);
if (mdic & E1000_MDIC_READY)
@@
-166,14
+170,14
@@
static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
}
/**
}
/**
- * e1000_write_phy_reg_mdic - Write MDI control register
+ * e1000
e
_write_phy_reg_mdic - Write MDI control register
* @hw: pointer to the HW structure
* @offset: register offset to write to
* @data: data to write to register at offset
*
* Writes data to MDI control register in the PHY at offset.
**/
* @hw: pointer to the HW structure
* @offset: register offset to write to
* @data: data to write to register at offset
*
* Writes data to MDI control register in the PHY at offset.
**/
-s
tatic s32 e1000
_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
+s
32 e1000e
_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
{
struct e1000_phy_info *phy = &hw->phy;
u32 i, mdic = 0;
{
struct e1000_phy_info *phy = &hw->phy;
u32 i, mdic = 0;
@@
-183,7
+187,8
@@
static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
return -E1000_ERR_PARAM;
}
return -E1000_ERR_PARAM;
}
- /* Set up Op-code, Phy Address, and register offset in the MDI
+ /*
+ * Set up Op-code, Phy Address, and register offset in the MDI
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
@@
-194,9
+199,13
@@
static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
ew32(MDIC, mdic);
ew32(MDIC, mdic);
- /* Poll the ready bit to see if the MDI read completed */
- for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
- udelay(5);
+ /*
+ * Poll the ready bit to see if the MDI read completed
+ * Increasing the time out as testing showed failures with
+ * the lower time out
+ */
+ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
+ udelay(50);
mdic = er32(MDIC);
if (mdic & E1000_MDIC_READY)
break;
mdic = er32(MDIC);
if (mdic & E1000_MDIC_READY)
break;
@@
-205,6
+214,10
@@
static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
hw_dbg(hw, "MDI Write did not complete\n");
return -E1000_ERR_PHY;
}
hw_dbg(hw, "MDI Write did not complete\n");
return -E1000_ERR_PHY;
}
+ if (mdic & E1000_MDIC_ERROR) {
+ hw_dbg(hw, "MDI Error\n");
+ return -E1000_ERR_PHY;
+ }
return 0;
}
return 0;
}
@@
-227,9
+240,8
@@
s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
- ret_val = e1000_read_phy_reg_mdic(hw,
- MAX_PHY_REG_ADDRESS & offset,
- data);
+ ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
+ data);
hw->phy.ops.release_phy(hw);
hw->phy.ops.release_phy(hw);
@@
-253,9
+265,8
@@
s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
- ret_val = e1000_write_phy_reg_mdic(hw,
- MAX_PHY_REG_ADDRESS & offset,
- data);
+ ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
+ data);
hw->phy.ops.release_phy(hw);
hw->phy.ops.release_phy(hw);
@@
-281,18
+292,17
@@
s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
return ret_val;
if (offset > MAX_PHY_MULTI_PAGE_REG) {
return ret_val;
if (offset > MAX_PHY_MULTI_PAGE_REG) {
- ret_val = e1000_write_phy_reg_mdic(hw,
- IGP01E1000_PHY_PAGE_SELECT,
- (u16)offset);
+ ret_val = e1000
e
_write_phy_reg_mdic(hw,
+
IGP01E1000_PHY_PAGE_SELECT,
+
(u16)offset);
if (ret_val) {
hw->phy.ops.release_phy(hw);
return ret_val;
}
}
if (ret_val) {
hw->phy.ops.release_phy(hw);
return ret_val;
}
}
- ret_val = e1000_read_phy_reg_mdic(hw,
- MAX_PHY_REG_ADDRESS & offset,
- data);
+ ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
+ data);
hw->phy.ops.release_phy(hw);
hw->phy.ops.release_phy(hw);
@@
-317,18
+327,17
@@
s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
return ret_val;
if (offset > MAX_PHY_MULTI_PAGE_REG) {
return ret_val;
if (offset > MAX_PHY_MULTI_PAGE_REG) {
- ret_val = e1000_write_phy_reg_mdic(hw,
- IGP01E1000_PHY_PAGE_SELECT,
- (u16)offset);
+ ret_val = e1000
e
_write_phy_reg_mdic(hw,
+
IGP01E1000_PHY_PAGE_SELECT,
+
(u16)offset);
if (ret_val) {
hw->phy.ops.release_phy(hw);
return ret_val;
}
}
if (ret_val) {
hw->phy.ops.release_phy(hw);
return ret_val;
}
}
- ret_val = e1000_write_phy_reg_mdic(hw,
- MAX_PHY_REG_ADDRESS & offset,
- data);
+ ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
+ data);
hw->phy.ops.release_phy(hw);
hw->phy.ops.release_phy(hw);
@@
-410,14
+419,17
@@
s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
s32 ret_val;
u16 phy_data;
s32 ret_val;
u16 phy_data;
- /* Enable CRS on T
X
. This must be set for half-duplex operation. */
+ /* Enable CRS on T
x
. This must be set for half-duplex operation. */
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
if (ret_val)
return ret_val;
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
if (ret_val)
return ret_val;
- phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
+ /* For newer PHYs this bit is downshift enable */
+ if (phy->type == e1000_phy_m88)
+ phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
- /* Options:
+ /*
+ * Options:
* MDI/MDI-X = 0 (default)
* 0 - Auto for all speeds
* 1 - MDI mode
* MDI/MDI-X = 0 (default)
* 0 - Auto for all speeds
* 1 - MDI mode
@@
-442,7
+454,8
@@
s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
break;
}
break;
}
- /* Options:
+ /*
+ * Options:
* disable_polarity_correction = 0 (default)
* Automatic Correction for Reversed Cable Polarity
* 0 - Disabled
* disable_polarity_correction = 0 (default)
* Automatic Correction for Reversed Cable Polarity
* 0 - Disabled
@@
-456,8
+469,9
@@
s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
- if (phy->revision < 4) {
- /* Force TX_CLK in the Extended PHY Specific Control Register
+ if ((phy->type == e1000_phy_m88) && (phy->revision < 4)) {
+ /*
+ * Force TX_CLK in the Extended PHY Specific Control Register
* to 25MHz clock.
*/
ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
* to 25MHz clock.
*/
ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
@@
-510,8
+524,11
@@
s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
return ret_val;
}
return ret_val;
}
- /* Wait 15ms for MAC to configure PHY from NVM settings. */
- msleep(15);
+ /*
+ * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
+ * timeout issues when LFS is enabled.
+ */
+ msleep(100);
/* disable lplu d0 during driver init */
ret_val = e1000_set_d0_lplu_state(hw, 0);
/* disable lplu d0 during driver init */
ret_val = e1000_set_d0_lplu_state(hw, 0);
@@
-544,19
+561,21
@@
s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
/* set auto-master slave resolution settings */
if (hw->mac.autoneg) {
/* set auto-master slave resolution settings */
if (hw->mac.autoneg) {
- /* when autonegotiation advertisement is only 1000Mbps then we
+ /*
+ * when autonegotiation advertisement is only 1000Mbps then we
* should disable SmartSpeed and enable Auto MasterSlave
* should disable SmartSpeed and enable Auto MasterSlave
- * resolution as hardware default. */
+ * resolution as hardware default.
+ */
if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
/* Disable SmartSpeed */
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
/* Disable SmartSpeed */
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
-
&data);
+ &data);
if (ret_val)
return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
if (ret_val)
return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
-
data);
+ data);
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
@@
-631,14
+650,16
@@
static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
return ret_val;
}
return ret_val;
}
- /* Need to parse both autoneg_advertised and fc and set up
+ /*
+ * Need to parse both autoneg_advertised and fc and set up
* the appropriate PHY registers. First we will parse for
* autoneg_advertised software override. Since we can advertise
* a plethora of combinations, we need to check each bit
* individually.
*/
* the appropriate PHY registers. First we will parse for
* autoneg_advertised software override. Since we can advertise
* a plethora of combinations, we need to check each bit
* individually.
*/
- /* First we clear all the 10/100 mb speed bits in the Auto-Neg
+ /*
+ * First we clear all the 10/100 mb speed bits in the Auto-Neg
* Advertisement Register (Address 4) and the 1000 mb speed bits in
* the 1000Base-T Control Register (Address 9).
*/
* Advertisement Register (Address 4) and the 1000 mb speed bits in
* the 1000Base-T Control Register (Address 9).
*/
@@
-684,7
+705,8
@@
static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
}
mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
}
- /* Check for a software override of the flow control settings, and
+ /*
+ * Check for a software override of the flow control settings, and
* setup the PHY advertisement registers accordingly. If
* auto-negotiation is enabled, then software will have to set the
* "PAUSE" bits to the correct value in the Auto-Negotiation
* setup the PHY advertisement registers accordingly. If
* auto-negotiation is enabled, then software will have to set the
* "PAUSE" bits to the correct value in the Auto-Negotiation
@@
-697,38
+719,42
@@
static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* but we do not support receiving pause frames).
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* but we do not support receiving pause frames).
- * 3: Both Rx and T
X
flow control (symmetric) are enabled.
+ * 3: Both Rx and T
x
flow control (symmetric) are enabled.
* other: No software override. The flow control configuration
* in the EEPROM is used.
*/
* other: No software override. The flow control configuration
* in the EEPROM is used.
*/
- switch (hw->
mac.fc
) {
+ switch (hw->
fc.type
) {
case e1000_fc_none:
case e1000_fc_none:
- /* Flow control (RX & TX) is completely disabled by a
+ /*
+ * Flow control (Rx & Tx) is completely disabled by a
* software over-ride.
*/
mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case e1000_fc_rx_pause:
* software over-ride.
*/
mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case e1000_fc_rx_pause:
- /* RX Flow control is enabled, and TX Flow control is
+ /*
+ * Rx Flow control is enabled, and Tx Flow control is
* disabled, by a software over-ride.
* disabled, by a software over-ride.
- *
/
-
/
* Since there really isn't a way to advertise that we are
- * capable of R
X
Pause ONLY, we will advertise that we
- * support both symmetric and asymmetric R
X
PAUSE. Later
+ *
+
* Since there really isn't a way to advertise that we are
+ * capable of R
x
Pause ONLY, we will advertise that we
+ * support both symmetric and asymmetric R
x
PAUSE. Later
* (in e1000e_config_fc_after_link_up) we will disable the
* hw's ability to send PAUSE frames.
*/
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case e1000_fc_tx_pause:
* (in e1000e_config_fc_after_link_up) we will disable the
* hw's ability to send PAUSE frames.
*/
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case e1000_fc_tx_pause:
- /* TX Flow control is enabled, and RX Flow control is
+ /*
+ * Tx Flow control is enabled, and Rx Flow control is
* disabled, by a software over-ride.
*/
mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
break;
case e1000_fc_full:
* disabled, by a software over-ride.
*/
mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
break;
case e1000_fc_full:
- /* Flow control (both RX and TX) is enabled by a software
+ /*
+ * Flow control (both Rx and Tx) is enabled by a software
* over-ride.
*/
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
* over-ride.
*/
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
@@
-759,7
+785,7
@@
static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
* Performs initial bounds checking on autoneg advertisement parameter, then
* configure to advertise the full capability. Setup the PHY to autoneg
* and restart the negotiation process between the link partner. If
* Performs initial bounds checking on autoneg advertisement parameter, then
* configure to advertise the full capability. Setup the PHY to autoneg
* and restart the negotiation process between the link partner. If
- *
wait_for_link
, then wait for autoneg to complete before exiting.
+ *
autoneg_wait_to_complete
, then wait for autoneg to complete before exiting.
**/
static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
{
**/
static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
{
@@
-767,12
+793,14
@@
static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
s32 ret_val;
u16 phy_ctrl;
s32 ret_val;
u16 phy_ctrl;
- /* Perform some bounds checking on the autoneg advertisement
+ /*
+ * Perform some bounds checking on the autoneg advertisement
* parameter.
*/
phy->autoneg_advertised &= phy->autoneg_mask;
* parameter.
*/
phy->autoneg_advertised &= phy->autoneg_mask;
- /* If autoneg_advertised is zero, we assume it was not defaulted
+ /*
+ * If autoneg_advertised is zero, we assume it was not defaulted
* by the calling code so we set to advertise full capability.
*/
if (phy->autoneg_advertised == 0)
* by the calling code so we set to advertise full capability.
*/
if (phy->autoneg_advertised == 0)
@@
-786,7
+814,8
@@
static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
}
hw_dbg(hw, "Restarting Auto-Neg\n");
}
hw_dbg(hw, "Restarting Auto-Neg\n");
- /* Restart auto-negotiation by setting the Auto Neg Enable bit and
+ /*
+ * Restart auto-negotiation by setting the Auto Neg Enable bit and
* the Auto Neg Restart bit in the PHY control register.
*/
ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
* the Auto Neg Restart bit in the PHY control register.
*/
ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
@@
-798,10
+827,11
@@
static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
- /* Does the user want to wait for Auto-Neg to complete here, or
+ /*
+ * Does the user want to wait for Auto-Neg to complete here, or
* check at a later time (for example, callback routine).
*/
* check at a later time (for example, callback routine).
*/
- if (phy->
wait_for_link
) {
+ if (phy->
autoneg_wait_to_complete
) {
ret_val = e1000_wait_autoneg(hw);
if (ret_val) {
hw_dbg(hw, "Error while waiting for "
ret_val = e1000_wait_autoneg(hw);
if (ret_val) {
hw_dbg(hw, "Error while waiting for "
@@
-830,14
+860,18
@@
s32 e1000e_setup_copper_link(struct e1000_hw *hw)
bool link;
if (hw->mac.autoneg) {
bool link;
if (hw->mac.autoneg) {
- /* Setup autoneg and flow control advertisement and perform
- * autonegotiation. */
+ /*
+ * Setup autoneg and flow control advertisement and perform
+ * autonegotiation.
+ */
ret_val = e1000_copper_link_autoneg(hw);
if (ret_val)
return ret_val;
} else {
ret_val = e1000_copper_link_autoneg(hw);
if (ret_val)
return ret_val;
} else {
- /* PHY will be set to 10H, 10F, 100H or 100F
- * depending on user settings. */
+ /*
+ * PHY will be set to 10H, 10F, 100H or 100F
+ * depending on user settings.
+ */
hw_dbg(hw, "Forcing Speed and Duplex\n");
ret_val = e1000_phy_force_speed_duplex(hw);
if (ret_val) {
hw_dbg(hw, "Forcing Speed and Duplex\n");
ret_val = e1000_phy_force_speed_duplex(hw);
if (ret_val) {
@@
-846,7
+880,8
@@
s32 e1000e_setup_copper_link(struct e1000_hw *hw)
}
}
}
}
- /* Check link status. Wait up to 100 microseconds for link to become
+ /*
+ * Check link status. Wait up to 100 microseconds for link to become
* valid.
*/
ret_val = e1000e_phy_has_link_generic(hw,
* valid.
*/
ret_val = e1000e_phy_has_link_generic(hw,
@@
-892,7
+927,8
@@
s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
- /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
+ /*
+ * Clear Auto-Crossover to force MDI manually. IGP requires MDI
* forced whenever speed and duplex are forced.
*/
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
* forced whenever speed and duplex are forced.
*/
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
@@
-910,7
+946,7
@@
s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
udelay(1);
udelay(1);
- if (phy->
wait_for_link
) {
+ if (phy->
autoneg_wait_to_complete
) {
hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
ret_val = e1000e_phy_has_link_generic(hw,
hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
ret_val = e1000e_phy_has_link_generic(hw,
@@
-942,7
+978,7
@@
s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
* Calls the PHY setup function to force speed and duplex. Clears the
* auto-crossover to force MDI manually. Resets the PHY to commit the
* changes. If time expires while waiting for link up, we reset the DSP.
* Calls the PHY setup function to force speed and duplex. Clears the
* auto-crossover to force MDI manually. Resets the PHY to commit the
* changes. If time expires while waiting for link up, we reset the DSP.
- * After reset, TX_CLK and CRS on T
X
must be set. Return successful upon
+ * After reset, TX_CLK and CRS on T
x
must be set. Return successful upon
* successful completion, else return corresponding error code.
**/
s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
* successful completion, else return corresponding error code.
**/
s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
@@
-952,7
+988,8
@@
s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
u16 phy_data;
bool link;
u16 phy_data;
bool link;
- /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
+ /*
+ * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
* forced whenever speed and duplex are forced.
*/
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
* forced whenever speed and duplex are forced.
*/
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@
-981,7
+1018,7
@@
s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
udelay(1);
udelay(1);
- if (phy->
wait_for_link
) {
+ if (phy->
autoneg_wait_to_complete
) {
hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
@@
-990,10
+1027,12
@@
s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
return ret_val;
if (!link) {
return ret_val;
if (!link) {
- /* We didn't get link.
+ /*
+ * We didn't get link.
* Reset the DSP and cross our fingers.
*/
* Reset the DSP and cross our fingers.
*/
- ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 0x001d);
+ ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
+ 0x001d);
if (ret_val)
return ret_val;
ret_val = e1000e_phy_reset_dsp(hw);
if (ret_val)
return ret_val;
ret_val = e1000e_phy_reset_dsp(hw);
@@
-1012,7
+1051,8
@@
s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
- /* Resetting the phy means we need to re-force TX_CLK in the
+ /*
+ * Resetting the phy means we need to re-force TX_CLK in the
* Extended PHY Specific Control Register to 25MHz clock from
* the reset value of 2.5MHz.
*/
* Extended PHY Specific Control Register to 25MHz clock from
* the reset value of 2.5MHz.
*/
@@
-1021,7
+1061,8
@@
s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
- /* In addition, we must re-enable CRS on Tx for both half and full
+ /*
+ * In addition, we must re-enable CRS on Tx for both half and full
* duplex.
*/
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
* duplex.
*/
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@
-1052,7
+1093,7
@@
void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
u32 ctrl;
/* Turn off flow control when forcing speed/duplex */
u32 ctrl;
/* Turn off flow control when forcing speed/duplex */
-
mac->fc
= e1000_fc_none;
+
hw->fc.type
= e1000_fc_none;
/* Force speed/duplex on the mac */
ctrl = er32(CTRL);
/* Force speed/duplex on the mac */
ctrl = er32(CTRL);
@@
-1120,35
+1161,35
@@
s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
if (!active) {
data &= ~IGP02E1000_PM_D3_LPLU;
if (!active) {
data &= ~IGP02E1000_PM_D3_LPLU;
- ret_val = e1e_wphy(hw,
- IGP02E1000_PHY_POWER_MGMT,
- data);
+ ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
- /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
+ /*
+ * LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
* during Dx states where the power conservation is most
* important. During driver activity we should enable
- * SmartSpeed, so performance is maintained. */
+ * SmartSpeed, so performance is maintained.
+ */
if (phy->smart_speed == e1000_smart_speed_on) {
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
if (phy->smart_speed == e1000_smart_speed_on) {
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
-
&data);
+ &data);
if (ret_val)
return ret_val;
data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
if (ret_val)
return ret_val;
data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
-
data);
+ data);
if (ret_val)
return ret_val;
} else if (phy->smart_speed == e1000_smart_speed_off) {
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
if (ret_val)
return ret_val;
} else if (phy->smart_speed == e1000_smart_speed_off) {
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
-
&data);
+ &data);
if (ret_val)
return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
if (ret_val)
return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
-
data);
+ data);
if (ret_val)
return ret_val;
}
if (ret_val)
return ret_val;
}
@@
-1173,7
+1214,7
@@
s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
}
/**
}
/**
- * e1000e_check_downshift - Checks whether a downshift in speed occured
+ * e1000e_check_downshift - Checks whether a downshift in speed occur
r
ed
* @hw: pointer to the HW structure
*
* Success returns 0, Failure returns 1
* @hw: pointer to the HW structure
*
* Success returns 0, Failure returns 1
@@
-1250,8
+1291,10
@@
static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
s32 ret_val;
u16 data, offset, mask;
s32 ret_val;
u16 data, offset, mask;
- /* Polarity is determined based on the speed of
- * our connection. */
+ /*
+ * Polarity is determined based on the speed of
+ * our connection.
+ */
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
if (ret_val)
return ret_val;
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
if (ret_val)
return ret_val;
@@
-1261,7
+1304,8
@@
static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
offset = IGP01E1000_PHY_PCS_INIT_REG;
mask = IGP01E1000_PHY_POLARITY_MASK;
} else {
offset = IGP01E1000_PHY_PCS_INIT_REG;
mask = IGP01E1000_PHY_POLARITY_MASK;
} else {
- /* This really only applies to 10Mbps since
+ /*
+ * This really only applies to 10Mbps since
* there is no polarity for 100Mbps (always 0).
*/
offset = IGP01E1000_PHY_PORT_STATUS;
* there is no polarity for 100Mbps (always 0).
*/
offset = IGP01E1000_PHY_PORT_STATUS;
@@
-1279,7
+1323,7
@@
static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
}
/**
}
/**
- * e1000_wait_autoneg - Wait for auto-neg comp
e
letion
+ * e1000_wait_autoneg - Wait for auto-neg completion
* @hw: pointer to the HW structure
*
* Waits for auto-negotiation to complete or for the auto-negotiation time
* @hw: pointer to the HW structure
*
* Waits for auto-negotiation to complete or for the auto-negotiation time
@@
-1303,7
+1347,8
@@
static s32 e1000_wait_autoneg(struct e1000_hw *hw)
msleep(100);
}
msleep(100);
}
- /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
+ /*
+ * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
* has completed.
*/
return ret_val;
* has completed.
*/
return ret_val;
@@
-1325,7
+1370,8
@@
s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
u16 i, phy_status;
for (i = 0; i < iterations; i++) {
u16 i, phy_status;
for (i = 0; i < iterations; i++) {
- /* Some PHYs require the PHY_STATUS register to be read
+ /*
+ * Some PHYs require the PHY_STATUS register to be read
* twice due to the link bit being sticky. No harm doing
* it across the board.
*/
* twice due to the link bit being sticky. No harm doing
* it across the board.
*/
@@
-1389,8
+1435,8
@@
s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
*
* The automatic gain control (agc) normalizes the amplitude of the
* received signal, adjusting for the attenuation produced by the
*
* The automatic gain control (agc) normalizes the amplitude of the
* received signal, adjusting for the attenuation produced by the
- * cable. By reading the AGC registers, which rep
e
resent the
- * cobination of course and fine gain value, the value can be put
+ * cable. By reading the AGC registers, which represent the
+ * co
m
bination of course and fine gain value, the value can be put
* into a lookup table to obtain the approximate cable length
* for each channel.
**/
* into a lookup table to obtain the approximate cable length
* for each channel.
**/
@@
-1413,10
+1459,12
@@
s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
if (ret_val)
return ret_val;
if (ret_val)
return ret_val;
- /* Getting bits 15:9, which represent the combination of
+ /*
+ * Getting bits 15:9, which represent the combination of
* course and fine gain values. The result is a number
* that can be put into the lookup table to obtain the
* course and fine gain values. The result is a number
* that can be put into the lookup table to obtain the
- * approximate cable length. */
+ * approximate cable length.
+ */
cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
IGP02E1000_AGC_LENGTH_MASK;
cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
IGP02E1000_AGC_LENGTH_MASK;
@@
-1467,7
+1515,7
@@
s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
u16 phy_data;
bool link;
u16 phy_data;
bool link;
- if (hw->media_type != e1000_media_type_copper) {
+ if (hw->
phy.
media_type != e1000_media_type_copper) {
hw_dbg(hw, "Phy info is only valid for copper media\n");
return -E1000_ERR_CONFIG;
}
hw_dbg(hw, "Phy info is only valid for copper media\n");
return -E1000_ERR_CONFIG;
}
@@
-1620,7
+1668,7
@@
s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
* Verify the reset block is not blocking us from resetting. Acquire
* semaphore (if necessary) and read/set/write the device control reset
* bit in the PHY. Wait the appropriate delay time for the device to
* Verify the reset block is not blocking us from resetting. Acquire
* semaphore (if necessary) and read/set/write the device control reset
* bit in the PHY. Wait the appropriate delay time for the device to
- * reset and relase the semaphore (if necessary).
+ * reset and rel
e
ase the semaphore (if necessary).
**/
s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
{
**/
s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
{
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