+* Default to --enable-compressed-debug-sections=gas for Linux/x86 targets.
+
+* Add --no-pad-sections to stop the assembler from padding the end of output
+ sections up to their alignment boundary.
+
+* Support for the ARMv8-M architecture has been added to the ARM port. Support
+ for the ARMv8-M Security and DSP Extensions has also been added to the ARM
+ port.
+
+* ARC backend accepts .extInstruction, .extCondCode, .extAuxRegister, and
+ .extCoreRegister pseudo-ops that allow an user to define custom
+ instructions, conditional codes, auxiliary and core registers.
+
+* Add a configure option --enable-elf-stt-common to decide whether ELF
+ assembler should generate common symbols with the STT_COMMON type by
+ default. Default to no.
+
+* New command line option --elf-stt-common= for ELF targets to control
+ whether to generate common symbols with the STT_COMMON type.
+
+* Add ability to set section flags and types via numeric values for ELF
+ based targets.
+
+* Add a configure option --enable-x86-relax-relocations to decide whether
+ x86 assembler should generate relax relocations by default. Default to
+ yes, except for x86 Solaris targets older than Solaris 12.
+
+* New command line option -mrelax-relocations= for x86 target to control
+ whether to generate relax relocations.
+
+* New command line option -mfence-as-lock-add=yes for x86 target to encode
+ lfence, mfence and sfence as "lock addl $0x0, (%[re]sp)".
+
+* Add assembly-time relaxation option for ARC cpus.
+
+* Add --with-cpu=TYPE configure option for ARC gas. This allows the default
+ cpu type to be adjusted at configure time.
+
+Changes in 2.26:
+
+* Add a configure option --enable-compressed-debug-sections={all,gas} to
+ decide whether DWARF debug sections should be compressed by default.
+
+* Add support for the ARC EM/HS, and ARC600/700 architectures. Remove
+ assembler support for Argonaut RISC architectures.
+
+* Symbol and label names can now be enclosed in double quotes (") which allows
+ them to contain characters that are not part of valid symbol names in high
+ level languages.
+
+* Added the correctly spelled -march=armv6kz, for ARMv6KZ support. The
+ previous spelling, -march=armv6zk, is still accepted.
+
+* Support for the ARMv8.1 architecture has been added to the Aarch64 port.
+ Support for the individual ARMv8.1 Adv.SIMD, LOR and PAN architecture
+ extensions has also been added to the Aarch64 port.
+
+* Support for the ARMv8.1 architecture has been added to the ARM port. Support
+ for the individual ARMv8.1 Adv.SIMD and PAN architecture extensions has also
+ been added to the ARM port.
+
+* Extend --compress-debug-sections option to support
+ --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF
+ targets.
+
+* --compress-debug-sections is turned on for Linux/x86 by default.
+
+Changes in 2.25:
+
+* Add support for the AVR Tiny microcontrollers.
+
+* Replace support for openrisc and or32 with support for or1k.
+
+* Enhanced the ARM port to accept the assembler output from the CodeComposer
+ Studio tool. Support is enabled via the new command line option -mccs.
+
+* Add support for the Andes NDS32.
+
+Changes in 2.24:
+
+* Add support for the Texas Instruments MSP430X processor.
+
+* Add -gdwarf-sections command line option to enable per-code-section
+ generation of DWARF .debug_line sections.
+
+* Add support for Altera Nios II.
+
+* Add support for the Imagination Technologies Meta processor.
+
+* Add support for the v850e3v5.
+
+* Remove assembler support for MIPS ECOFF targets.
+
+Changes in 2.23:
+
+* Add support for the 64-bit ARM architecture: AArch64.
+
+* Add support for S12X processor.
+
+* Add support for the VLE extension to the PowerPC architecture.
+
+* Add support for the Freescale XGATE architecture.
+
+* Add support for .bundle_align_mode, .bundle_lock, and .bundle_unlock
+ directives. These are currently available only for x86 and ARM targets.
+
+* Add support for the Renesas RL78 architecture.
+
+* Add support for the Adapteva EPIPHANY architecture.
+
+* For x86, allow 'rep bsf', 'rep bsr', and 'rep ret' syntax.
+
+Changes in 2.22:
+
+* Add support for the Tilera TILEPro and TILE-Gx architectures.
+
+Changes in 2.21:
+
+* Gas no longer requires doubling of ampersands in macros.
+
+* Add support for the TMS320C6000 (TI C6X) processor family.
+
+* GAS now understands an extended syntax in the .section directive flags
+ for COFF targets that allows the section's alignment to be specified. This
+ feature has also been backported to the 2.20 release series, starting with
+ 2.20.1.
+
+* Add support for the Renesas RX processor.
+
+* New command line option, --compress-debug-sections, which requests
+ compression of DWARF debug information sections in the relocatable output
+ file. Compressed debug sections are supported by readelf, objdump, and
+ gold, but not currently by Gnu ld.
+
+Changes in 2.20:
+
+* Added support for v850e2 and v850e2v3.
+
+* GNU/Linux targets now supports "gnu_unique_object" as a value in the .type
+ pseudo op. It marks the symbol as being globally unique in the entire
+ process.
+
+* ARM assembler now supports .inst[.nw] pseudo-ops to insert opcodes specified
+ in binary rather than text.
+
+* Add support for common symbol alignment to PE formats.
+
+* Add support for the new discriminator column in the DWARF line table,
+ with a discriminator operand for the .loc directive.
+
+* Add support for Sunplus score architecture.
+
+* The .type pseudo-op now accepts a type of STT_GNU_IFUNC which can be used to
+ indicate that if the symbol is the target of a relocation, its value should
+ not be use. Instead the function should be invoked and its result used as
+ the value.
+
+* Add support for Lattice Mico32 (lm32) architecture.
+
+* Add support for Xilinx MicroBlaze architecture.
+
+Changes in 2.19:
+
+* New pseudo op .cfi_val_encoded_addr, to record constant addresses in unwind
+ tables without runtime relocation.
+
+* New command line option, -h-tick-hex, for sh, m32c, and h8/300 targets, which
+ adds compatibility with H'00 style hex constants.
+