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This fixes a bug in the ARm assembler where an immediate operand larger than 4 bits...
[deliverable/binutils-gdb.git]
/
gas
/
config
/
rl78-parse.y
diff --git
a/gas/config/rl78-parse.y
b/gas/config/rl78-parse.y
index 1f01920ce0f9a3f0c6647f3d69d971bcec62196b..cbd2ec4fc23eb859fddf9b491791ab0fe0f7dbe1 100644
(file)
--- a/
gas/config/rl78-parse.y
+++ b/
gas/config/rl78-parse.y
@@
-1,5
+1,5
@@
/* rl78-parse.y Renesas RL78 parser
/* rl78-parse.y Renesas RL78 parser
- Copyright
2011-2013
Free Software Foundation, Inc.
+ Copyright
(C) 2011-2019
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
This file is part of GAS, the GNU Assembler.
@@
-96,6
+96,8
@@
static int rl78_bit_insn = 0;
#define NOT_SADDR rl78_error ("Expression not 0xFFE20 to 0xFFF1F")
#define SA(e) if (!expr_is_saddr (e)) NOT_SADDR;
#define NOT_SADDR rl78_error ("Expression not 0xFFE20 to 0xFFF1F")
#define SA(e) if (!expr_is_saddr (e)) NOT_SADDR;
+#define SET_SA(e) e.X_md = BFD_RELOC_RL78_SADDR
+
#define NOT_SFR rl78_error ("Expression not 0xFFF00 to 0xFFFFF")
#define SFR(e) if (!expr_is_sfr (e)) NOT_SFR;
#define NOT_SFR rl78_error ("Expression not 0xFFF00 to 0xFFFFF")
#define SFR(e) if (!expr_is_sfr (e)) NOT_SFR;
@@
-105,6
+107,10
@@
static int rl78_bit_insn = 0;
#define WA(x) if (!expr_is_word_aligned (x)) rl78_error ("Expression not word-aligned");
#define WA(x) if (!expr_is_word_aligned (x)) rl78_error ("Expression not word-aligned");
+#define ISA_G10(s) if (!rl78_isa_g10()) rl78_error (s " is only supported on the G10")
+#define ISA_G13(s) if (!rl78_isa_g13()) rl78_error (s " is only supported on the G13")
+#define ISA_G14(s) if (!rl78_isa_g14()) rl78_error (s " is only supported on the G14")
+
static void check_expr_is_bit_index (expressionS);
#define Bit(e) check_expr_is_bit_index (e);
static void check_expr_is_bit_index (expressionS);
#define Bit(e) check_expr_is_bit_index (e);
@@
-203,7
+209,7
@@
statement :
{ B1 (0x0c|$1); O1 ($5); }
| addsub EXPR {SA($2)} ',' '#' EXPR
{ B1 (0x0c|$1); O1 ($5); }
| addsub EXPR {SA($2)} ',' '#' EXPR
- { B1 (0x0a|$1); O1 ($2); O1 ($6); }
+ { B1 (0x0a|$1);
SET_SA ($2);
O1 ($2); O1 ($6); }
| addsub A ',' A
{ B2 (0x61, 0x01|$1); }
| addsub A ',' A
{ B2 (0x61, 0x01|$1); }
@@
-215,7
+221,7
@@
statement :
{ B2 (0x61, 0x00|$1); F ($2, 13, 3); }
| addsub A ',' EXPR {SA($4)}
{ B2 (0x61, 0x00|$1); F ($2, 13, 3); }
| addsub A ',' EXPR {SA($4)}
- { B1 (0x0b|$1); O1 ($4); }
+ { B1 (0x0b|$1);
SET_SA ($4);
O1 ($4); }
| addsub A ',' opt_es '!' EXPR
{ B1 (0x0f|$1); O2 ($6); rl78_linkrelax_addr16 (); }
| addsub A ',' opt_es '!' EXPR
{ B1 (0x0f|$1); O2 ($6); rl78_linkrelax_addr16 (); }
@@
-232,8
+238,6
@@
statement :
| addsub A ',' opt_es '[' HL '+' C ']'
{ B2 (0x61, 0x82|$1); }
| addsub A ',' opt_es '[' HL '+' C ']'
{ B2 (0x61, 0x82|$1); }
-
-
| addsub opt_es '!' EXPR ',' '#' EXPR
{ if ($1 != 0x40)
{ rl78_error ("Only CMP takes these operands"); }
| addsub opt_es '!' EXPR ',' '#' EXPR
{ if ($1 != 0x40)
{ rl78_error ("Only CMP takes these operands"); }
@@
-250,7
+254,7
@@
statement :
{ B1 (0x01|$1); F ($4, 5, 2); }
| addsubw AX ',' EXPR {SA($4)}
{ B1 (0x01|$1); F ($4, 5, 2); }
| addsubw AX ',' EXPR {SA($4)}
- { B1 (0x06|$1); O1 ($4); }
+ { B1 (0x06|$1);
SET_SA ($4);
O1 ($4); }
| addsubw AX ',' opt_es '!' EXPR
{ B1 (0x02|$1); O2 ($6); rl78_linkrelax_addr16 (); }
| addsubw AX ',' opt_es '!' EXPR
{ B1 (0x02|$1); O2 ($6); rl78_linkrelax_addr16 (); }
@@
-259,7
+263,7
@@
statement :
{ B2 (0x61, 0x09|$1); O1 ($8); }
| addsubw AX ',' opt_es '[' HL ']'
{ B2 (0x61, 0x09|$1); O1 ($8); }
| addsubw AX ',' opt_es '[' HL ']'
- { B
4 (0x61, 0x09|$1, 0
, 0); }
+ { B
3 (0x61, 0x09|$1
, 0); }
| addsubw SP ',' '#' EXPR
{ B1 ($1 ? 0x20 : 0x10); O1 ($5);
| addsubw SP ',' '#' EXPR
{ B1 ($1 ? 0x20 : 0x10); O1 ($5);
@@
-276,7
+280,7
@@
statement :
{ if (expr_is_sfr ($4))
{ B2 (0x71, 0x08|$1); FE ($6, 9, 3); O1 ($4); }
else if (expr_is_saddr ($4))
{ if (expr_is_sfr ($4))
{ B2 (0x71, 0x08|$1); FE ($6, 9, 3); O1 ($4); }
else if (expr_is_saddr ($4))
- { B2 (0x71, 0x00|$1); FE ($6, 9, 3); O1 ($4); }
+ { B2 (0x71, 0x00|$1); FE ($6, 9, 3);
SET_SA ($4);
O1 ($4); }
else
NOT_SFR_OR_SADDR;
}
else
NOT_SFR_OR_SADDR;
}
@@
-290,22
+294,22
@@
statement :
/* ---------------------------------------------------------------------- */
| BC '$' EXPR
/* ---------------------------------------------------------------------- */
| BC '$' EXPR
- { B1 (0xdc); PC1 ($3); }
+ { B1 (0xdc); PC1 ($3);
rl78_linkrelax_branch ();
}
| BNC '$' EXPR
| BNC '$' EXPR
- { B1 (0xde); PC1 ($3); }
+ { B1 (0xde); PC1 ($3);
rl78_linkrelax_branch ();
}
| BZ '$' EXPR
| BZ '$' EXPR
- { B1 (0xdd); PC1 ($3); }
+ { B1 (0xdd); PC1 ($3);
rl78_linkrelax_branch ();
}
| BNZ '$' EXPR
| BNZ '$' EXPR
- { B1 (0xdf); PC1 ($3); }
+ { B1 (0xdf); PC1 ($3);
rl78_linkrelax_branch ();
}
| BH '$' EXPR
| BH '$' EXPR
- { B2 (0x61, 0xc3); PC1 ($3); }
+ { B2 (0x61, 0xc3); PC1 ($3);
rl78_linkrelax_branch ();
}
| BNH '$' EXPR
| BNH '$' EXPR
- { B2 (0x61, 0xd3); PC1 ($3); }
+ { B2 (0x61, 0xd3); PC1 ($3);
rl78_linkrelax_branch ();
}
/* ---------------------------------------------------------------------- */
/* ---------------------------------------------------------------------- */
@@
-316,7
+320,7
@@
statement :
{ if (expr_is_sfr ($2))
{ B2 (0x31, 0x80|$1); FE ($4, 9, 3); O1 ($2); PC1 ($7); }
else if (expr_is_saddr ($2))
{ if (expr_is_sfr ($2))
{ B2 (0x31, 0x80|$1); FE ($4, 9, 3); O1 ($2); PC1 ($7); }
else if (expr_is_saddr ($2))
- { B2 (0x31, 0x00|$1); FE ($4, 9, 3); O1 ($2); PC1 ($7); }
+ { B2 (0x31, 0x00|$1); FE ($4, 9, 3);
SET_SA ($2);
O1 ($2); PC1 ($7); }
else
NOT_SFR_OR_SADDR;
}
else
NOT_SFR_OR_SADDR;
}
@@
-333,7
+337,7
@@
statement :
{ B2 (0x61, 0xcb); }
| BR '$' EXPR
{ B2 (0x61, 0xcb); }
| BR '$' EXPR
- { B1 (0xef); PC1 ($3); }
+ { B1 (0xef); PC1 ($3);
rl78_linkrelax_branch ();
}
| BR '$' '!' EXPR
{ B1 (0xee); PC2 ($4); rl78_linkrelax_branch (); }
| BR '$' '!' EXPR
{ B1 (0xee); PC2 ($4); rl78_linkrelax_branch (); }
@@
-397,7
+401,7
@@
statement :
{ if (expr_is_sfr ($2))
{ B2 (0x71, 0x0a|$1); FE ($4, 9, 3); O1 ($2); }
else if (expr_is_saddr ($2))
{ if (expr_is_sfr ($2))
{ B2 (0x71, 0x0a|$1); FE ($4, 9, 3); O1 ($2); }
else if (expr_is_saddr ($2))
- { B2 (0x71, 0x02|$1); FE ($4, 9, 3); O1 ($2); }
+ { B2 (0x71, 0x02|$1); FE ($4, 9, 3);
SET_SA ($2);
O1 ($2); }
else
NOT_SFR_OR_SADDR;
}
else
NOT_SFR_OR_SADDR;
}
@@
-423,7
+427,7
@@
statement :
{ B1 (0xe2|$1); }
| oneclrb EXPR {SA($2)}
{ B1 (0xe2|$1); }
| oneclrb EXPR {SA($2)}
- { B1 (0xe4|$1); O1 ($2); }
+ { B1 (0xe4|$1);
SET_SA ($2);
O1 ($2); }
| oneclrb opt_es '!' EXPR
{ B1 (0xe5|$1); O2 ($4); rl78_linkrelax_addr16 (); }
| oneclrb opt_es '!' EXPR
{ B1 (0xe5|$1); O2 ($4); rl78_linkrelax_addr16 (); }
@@
-450,7
+454,7
@@
statement :
{ B1 (0xd2); }
| CMP0 EXPR {SA($2)}
{ B1 (0xd2); }
| CMP0 EXPR {SA($2)}
- { B1 (0xd4); O1 ($2); }
+ { B1 (0xd4);
SET_SA ($2);
O1 ($2); }
| CMP0 opt_es '!' EXPR
{ B1 (0xd5); O2 ($4); rl78_linkrelax_addr16 (); }
| CMP0 opt_es '!' EXPR
{ B1 (0xd5); O2 ($4); rl78_linkrelax_addr16 (); }
@@
-466,7
+470,7
@@
statement :
{ B1 (0x80|$1); F ($2, 5, 3); }
| incdec EXPR {SA($2)}
{ B1 (0x80|$1); F ($2, 5, 3); }
| incdec EXPR {SA($2)}
- { B1 (0xa4|$1); O1 ($2); }
+ { B1 (0xa4|$1);
SET_SA ($2);
O1 ($2); }
| incdec '!' EXPR
{ B1 (0xa0|$1); O2 ($3); rl78_linkrelax_addr16 (); }
| incdec ES ':' '!' EXPR
| incdec '!' EXPR
{ B1 (0xa0|$1); O2 ($3); rl78_linkrelax_addr16 (); }
| incdec ES ':' '!' EXPR
@@
-482,7
+486,7
@@
statement :
{ B1 (0xa1|$1); F ($2, 5, 2); }
| incdecw EXPR {SA($2)}
{ B1 (0xa1|$1); F ($2, 5, 2); }
| incdecw EXPR {SA($2)}
- { B1 (0xa6|$1); O1 ($2); }
+ { B1 (0xa6|$1);
SET_SA ($2);
O1 ($2); }
| incdecw opt_es '!' EXPR
{ B1 (0xa2|$1); O2 ($4); rl78_linkrelax_addr16 (); }
| incdecw opt_es '!' EXPR
{ B1 (0xa2|$1); O2 ($4); rl78_linkrelax_addr16 (); }
@@
-500,16
+504,16
@@
statement :
/* ---------------------------------------------------------------------- */
/* ---------------------------------------------------------------------- */
- | MULHU
+ | MULHU
{ ISA_G14 ("MULHU"); }
{ B3 (0xce, 0xfb, 0x01); }
{ B3 (0xce, 0xfb, 0x01); }
- | MULH
+ | MULH
{ ISA_G14 ("MULH"); }
{ B3 (0xce, 0xfb, 0x02); }
| MULU X
{ B1 (0xd6); }
{ B3 (0xce, 0xfb, 0x02); }
| MULU X
{ B1 (0xd6); }
- | DIVHU
+ | DIVHU
{ ISA_G14 ("DIVHU"); }
{ B3 (0xce, 0xfb, 0x03); }
/* Note that the DIVWU encoding was changed from [0xce,0xfb,0x04] to
{ B3 (0xce, 0xfb, 0x03); }
/* Note that the DIVWU encoding was changed from [0xce,0xfb,0x04] to
@@
-517,13
+521,13
@@
statement :
with the same version number, but varying encodings. The version
here matches the hardware. */
with the same version number, but varying encodings. The version
here matches the hardware. */
- | DIVWU
+ | DIVWU
{ ISA_G14 ("DIVWU"); }
{ B3 (0xce, 0xfb, 0x0b); }
{ B3 (0xce, 0xfb, 0x0b); }
- | MACHU
+ | MACHU
{ ISA_G14 ("MACHU"); }
{ B3 (0xce, 0xfb, 0x05); }
{ B3 (0xce, 0xfb, 0x05); }
- | MACH
+ | MACH
{ ISA_G14 ("MACH"); }
{ B3 (0xce, 0xfb, 0x06); }
/* ---------------------------------------------------------------------- */
{ B3 (0xce, 0xfb, 0x06); }
/* ---------------------------------------------------------------------- */
@@
-552,7
+556,7
@@
statement :
{ if (expr_is_sfr ($3))
{ B1 (0xce); O1 ($3); O1 ($6); }
else if (expr_is_saddr ($3))
{ if (expr_is_sfr ($3))
{ B1 (0xce); O1 ($3); O1 ($6); }
else if (expr_is_saddr ($3))
- { B1 (0xcd); O1 ($3); O1 ($6); }
+ { B1 (0xcd);
SET_SA ($3);
O1 ($3); O1 ($6); }
else
NOT_SFR_OR_SADDR;
}
else
NOT_SFR_OR_SADDR;
}
@@
-573,7
+577,7
@@
statement :
{ if (expr_is_sfr ($3))
{ B1 (0x9e); O1 ($3); }
else if (expr_is_saddr ($3))
{ if (expr_is_sfr ($3))
{ B1 (0x9e); O1 ($3); }
else if (expr_is_saddr ($3))
- { B1 (0x9d); O1 ($3); }
+ { B1 (0x9d);
SET_SA ($3);
O1 ($3); }
else
NOT_SFR_OR_SADDR;
}
else
NOT_SFR_OR_SADDR;
}
@@
-592,7
+596,7
@@
statement :
| MOV A ',' opt_es EXPR {NOT_ES}
{ if (expr_is_saddr ($5))
| MOV A ',' opt_es EXPR {NOT_ES}
{ if (expr_is_saddr ($5))
- { B1 (0x8d); O1 ($5); }
+ { B1 (0x8d);
SET_SA ($5);
O1 ($5); }
else if (expr_is_sfr ($5))
{ B1 (0x8e); O1 ($5); }
else
else if (expr_is_sfr ($5))
{ B1 (0x8e); O1 ($5); }
else
@@
-600,7
+604,7
@@
statement :
}
| MOV regb_na ',' opt_es EXPR {SA($5)} {NOT_ES}
}
| MOV regb_na ',' opt_es EXPR {SA($5)} {NOT_ES}
- { B1 (0xc8|reg_xbc($2)); O1 ($5); }
+ { B1 (0xc8|reg_xbc($2));
SET_SA ($5);
O1 ($5); }
| MOV A ',' sfr
{ B2 (0x8e, $4); }
| MOV A ',' sfr
{ B2 (0x8e, $4); }
@@
-616,7
+620,7
@@
statement :
{ if ($2 != 0xfd)
rl78_error ("Only ES allowed here");
else
{ if ($2 != 0xfd)
rl78_error ("Only ES allowed here");
else
- { B2 (0x61, 0xb8); O1 ($5); }
+ { B2 (0x61, 0xb8);
SET_SA ($5);
O1 ($5); }
}
| MOV A ',' opt_es '[' DE ']'
}
| MOV A ',' opt_es '[' DE ']'
@@
-719,7
+723,7
@@
statement :
| mov1 CY ',' EXPR '.' EXPR
{ if (expr_is_saddr ($4))
| mov1 CY ',' EXPR '.' EXPR
{ if (expr_is_saddr ($4))
- { B2 (0x71, 0x04); FE ($6, 9, 3); O1 ($4); }
+ { B2 (0x71, 0x04); FE ($6, 9, 3);
SET_SA ($4);
O1 ($4); }
else if (expr_is_sfr ($4))
{ B2 (0x71, 0x0c); FE ($6, 9, 3); O1 ($4); }
else
else if (expr_is_sfr ($4))
{ B2 (0x71, 0x0c); FE ($6, 9, 3); O1 ($4); }
else
@@
-737,7
+741,7
@@
statement :
| mov1 EXPR '.' EXPR ',' CY
{ if (expr_is_saddr ($2))
| mov1 EXPR '.' EXPR ',' CY
{ if (expr_is_saddr ($2))
- { B2 (0x71, 0x01); FE ($4, 9, 3); O1 ($2); }
+ { B2 (0x71, 0x01); FE ($4, 9, 3);
SET_SA ($2);
O1 ($2); }
else if (expr_is_sfr ($2))
{ B2 (0x71, 0x09); FE ($4, 9, 3); O1 ($2); }
else
else if (expr_is_sfr ($2))
{ B2 (0x71, 0x09); FE ($4, 9, 3); O1 ($2); }
else
@@
-768,7
+772,7
@@
statement :
| MOVW opt_es EXPR ',' '#' EXPR {NOT_ES}
{ if (expr_is_saddr ($3))
| MOVW opt_es EXPR ',' '#' EXPR {NOT_ES}
{ if (expr_is_saddr ($3))
- { B1 (0xc9); O1 ($3); O2 ($6); }
+ { B1 (0xc9);
SET_SA ($3);
O1 ($3); O2 ($6); }
else if (expr_is_sfr ($3))
{ B1 (0xcb); O1 ($3); O2 ($6); }
else
else if (expr_is_sfr ($3))
{ B1 (0xcb); O1 ($3); O2 ($6); }
else
@@
-777,7
+781,7
@@
statement :
| MOVW AX ',' opt_es EXPR {NOT_ES}
{ if (expr_is_saddr ($5))
| MOVW AX ',' opt_es EXPR {NOT_ES}
{ if (expr_is_saddr ($5))
- { B1 (0xad); O1 ($5); WA($5); }
+ { B1 (0xad);
SET_SA ($5);
O1 ($5); WA($5); }
else if (expr_is_sfr ($5))
{ B1 (0xae); O1 ($5); WA($5); }
else
else if (expr_is_sfr ($5))
{ B1 (0xae); O1 ($5); WA($5); }
else
@@
-786,7
+790,7
@@
statement :
| MOVW opt_es EXPR ',' AX {NOT_ES}
{ if (expr_is_saddr ($3))
| MOVW opt_es EXPR ',' AX {NOT_ES}
{ if (expr_is_saddr ($3))
- { B1 (0xbd); O1 ($3); WA($3); }
+ { B1 (0xbd);
SET_SA ($3);
O1 ($3); WA($3); }
else if (expr_is_sfr ($3))
{ B1 (0xbe); O1 ($3); WA($3); }
else
else if (expr_is_sfr ($3))
{ B1 (0xbe); O1 ($3); WA($3); }
else
@@
-866,7
+870,7
@@
statement :
{ B2 (0xb8, 0); }
| MOVW regw_na ',' EXPR {SA($4)}
{ B2 (0xb8, 0); }
| MOVW regw_na ',' EXPR {SA($4)}
- { B1 (0xca); F ($2, 2, 2); O1 ($4); WA($4); }
+ { B1 (0xca); F ($2, 2, 2);
SET_SA ($4);
O1 ($4); WA($4); }
| MOVW regw_na ',' opt_es '!' EXPR
{ B1 (0xcb); F ($2, 2, 2); O2 ($6); WA($6); rl78_linkrelax_addr16 (); }
| MOVW regw_na ',' opt_es '!' EXPR
{ B1 (0xcb); F ($2, 2, 2); O2 ($6); WA($6); rl78_linkrelax_addr16 (); }
@@
-1018,22
+1022,22
@@
statement :
/* ---------------------------------------------------------------------- */
| SKC
/* ---------------------------------------------------------------------- */
| SKC
- { B2 (0x61, 0xc8); rl78_
linkrelax_branch (
); }
+ { B2 (0x61, 0xc8); rl78_
relax (RL78_RELAX_BRANCH, 0
); }
| SKH
| SKH
- { B2 (0x61, 0xe3); rl78_
linkrelax_branch (
); }
+ { B2 (0x61, 0xe3); rl78_
relax (RL78_RELAX_BRANCH, 0
); }
| SKNC
| SKNC
- { B2 (0x61, 0xd8); rl78_
linkrelax_branch (
); }
+ { B2 (0x61, 0xd8); rl78_
relax (RL78_RELAX_BRANCH, 0
); }
| SKNH
| SKNH
- { B2 (0x61, 0xf3); rl78_
linkrelax_branch (
); }
+ { B2 (0x61, 0xf3); rl78_
relax (RL78_RELAX_BRANCH, 0
); }
| SKNZ
| SKNZ
- { B2 (0x61, 0xf8); rl78_
linkrelax_branch (
); }
+ { B2 (0x61, 0xf8); rl78_
relax (RL78_RELAX_BRANCH, 0
); }
| SKZ
| SKZ
- { B2 (0x61, 0xe8); rl78_
linkrelax_branch (
); }
+ { B2 (0x61, 0xe8); rl78_
relax (RL78_RELAX_BRANCH, 0
); }
/* ---------------------------------------------------------------------- */
/* ---------------------------------------------------------------------- */
@@
-1074,7
+1078,7
@@
statement :
{ if (expr_is_sfr ($4))
{ B2 (0x61, 0xab); O1 ($4); }
else if (expr_is_saddr ($4))
{ if (expr_is_sfr ($4))
{ B2 (0x61, 0xab); O1 ($4); }
else if (expr_is_saddr ($4))
- { B2 (0x61, 0xa8); O1 ($4); }
+ { B2 (0x61, 0xa8);
SET_SA ($4);
O1 ($4); }
else
NOT_SFR_OR_SADDR;
}
else
NOT_SFR_OR_SADDR;
}
@@
-1153,12
+1157,12
@@
addsubw : ADDW { $$ = 0x00; }
;
andor1 : AND1 { $$ = 0x05; rl78_bit_insn = 1; }
;
andor1 : AND1 { $$ = 0x05; rl78_bit_insn = 1; }
- | OR1 { $$ = 0x06; rl78_bit_insn = 1;}
+ | OR1 { $$ = 0x06; rl78_bit_insn = 1;
}
| XOR1 { $$ = 0x07; rl78_bit_insn = 1; }
;
| XOR1 { $$ = 0x07; rl78_bit_insn = 1; }
;
-bt_bf : BT { $$ = 0x02; rl78_bit_insn = 1;}
- | BF { $$ = 0x04; rl78_bit_insn = 1; }
+bt_bf : BT { $$ = 0x02; rl78_bit_insn = 1;
rl78_linkrelax_branch ();
}
+ | BF { $$ = 0x04; rl78_bit_insn = 1;
rl78_linkrelax_branch ();
}
| BTCLR { $$ = 0x00; rl78_bit_insn = 1; }
;
| BTCLR { $$ = 0x00; rl78_bit_insn = 1; }
;
@@
-1527,7
+1531,7
@@
expr_is_saddr (expressionS exp)
unsigned long v;
if (exp.X_op != O_constant)
unsigned long v;
if (exp.X_op != O_constant)
- return
0
;
+ return
1
;
v = exp.X_add_number;
if (0xFFE20 <= v && v <= 0xFFF1F)
v = exp.X_add_number;
if (0xFFE20 <= v && v <= 0xFFF1F)
@@
-1547,7
+1551,7
@@
expr_is_word_aligned (expressionS exp)
if (v & 1)
return 0;
return 1;
if (v & 1)
return 0;
return 1;
-
+
}
static void
}
static void
@@
-1594,5
+1598,3
@@
check_expr_is_const (expressionS e, int vmin, int vmax)
}
return 1;
}
}
return 1;
}
-
-
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