2007-08-09 Paul Brook <paul@codesourcery.com>

[deliverable/binutils-gdb.git] / gas / config / tc-arm.c

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 45b8d2e85dfc3dd385bd31cdbb96a6254c9d08ff..117fe16d31b686a5f003f3ee304932976a1ebffb 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -1,6 +1,6 @@
 /* tc-arm.c -- Assemble for the ARM
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
 /* tc-arm.c -- Assemble for the ARM
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,

-   2004, 2005, 2006
+   2004, 2005, 2006, 2007

    Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
        Modified by David Taylor (dtaylor@armltd.co.uk)
    Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
        Modified by David Taylor (dtaylor@armltd.co.uk)


@@ -12,7 +12,7 @@
 
    GAS is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
 
    GAS is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by

-   the Free Software Foundation; either version 2, or (at your option)
+   the Free Software Foundation; either version 3, or (at your option)

    any later version.
 
    GAS is distributed in the hope that it will be useful,
    any later version.
 
    GAS is distributed in the hope that it will be useful,


@@ -333,6 +333,7 @@ struct arm_it
     unsigned immisreg  : 1;  /* .imm field is a second register.  */
     unsigned isscalar   : 1;  /* Operand is a (Neon) scalar.  */
     unsigned immisalign : 1;  /* Immediate is an alignment specifier.  */
     unsigned immisreg  : 1;  /* .imm field is a second register.  */
     unsigned isscalar   : 1;  /* Operand is a (Neon) scalar.  */
     unsigned immisalign : 1;  /* Immediate is an alignment specifier.  */

+    unsigned immisfloat : 1;  /* Immediate was parsed as a float.  */

     /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
        instructions. This allows us to disambiguate ARM <-> vector insns.  */
     unsigned regisimm   : 1;  /* 64-bit immediate, reg forms high 32 bits.  */
     /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
        instructions. This allows us to disambiguate ARM <-> vector insns.  */
     unsigned regisimm   : 1;  /* 64-bit immediate, reg forms high 32 bits.  */


@@ -554,6 +555,8 @@ struct asm_opcode
 #define OPCODE_MASK    0xfe1fffff
 #define V4_STR_BIT     0x00000020
 
 #define OPCODE_MASK    0xfe1fffff
 #define V4_STR_BIT     0x00000020
 

+#define T2_SUBS_PC_LR  0xf3de8f00
+

 #define DATA_OP_SHIFT  21
 
 #define T2_OPCODE_MASK 0xfe1fffff
 #define DATA_OP_SHIFT  21
 
 #define T2_OPCODE_MASK 0xfe1fffff


@@ -1968,7 +1971,7 @@ insert_reg_alias (char *str, int number, int type)
       else if (new->number != number || new->type != type)
        as_warn (_("ignoring redefinition of register alias '%s'"), str);
 
       else if (new->number != number || new->type != type)
        as_warn (_("ignoring redefinition of register alias '%s'"), str);
 

-      return 0;
+      return NULL;

     }
 
   name = xstrdup (str);
     }
 
   name = xstrdup (str);


@@ -2010,9 +2013,9 @@ insert_neon_reg_alias (char *str, int number, int type,
        new_register_name .req existing_register_name
 
    If we find one, or if it looks sufficiently like one that we want to
        new_register_name .req existing_register_name
 
    If we find one, or if it looks sufficiently like one that we want to

-   handle any error here, return non-zero.  Otherwise return zero.  */
+   handle any error here, return TRUE.  Otherwise return FALSE.  */

 
 

-static int
+static bfd_boolean

 create_register_alias (char * newname, char *p)
 {
   struct reg_entry *old;
 create_register_alias (char * newname, char *p)
 {
   struct reg_entry *old;


@@ -2023,17 +2026,17 @@ create_register_alias (char * newname, char *p)
      collapsed to single spaces.  */
   oldname = p;
   if (strncmp (oldname, " .req ", 6) != 0)
      collapsed to single spaces.  */
   oldname = p;
   if (strncmp (oldname, " .req ", 6) != 0)

-    return 0;
+    return FALSE;

 
   oldname += 6;
   if (*oldname == '\0')
 
   oldname += 6;
   if (*oldname == '\0')

-    return 0;
+    return FALSE;

 
   old = hash_find (arm_reg_hsh, oldname);
   if (!old)
     {
       as_warn (_("unknown register '%s' -- .req ignored"), oldname);
 
   old = hash_find (arm_reg_hsh, oldname);
   if (!old)
     {
       as_warn (_("unknown register '%s' -- .req ignored"), oldname);

-      return 1;
+      return TRUE;

     }
 
   /* If TC_CASE_SENSITIVE is defined, then newname already points to
     }
 
   /* If TC_CASE_SENSITIVE is defined, then newname already points to


@@ -2053,21 +2056,34 @@ create_register_alias (char * newname, char *p)
   /* Create aliases under the new name as stated; an all-lowercase
      version of the new name; and an all-uppercase version of the new
      name.  */
   /* Create aliases under the new name as stated; an all-lowercase
      version of the new name; and an all-uppercase version of the new
      name.  */

-  insert_reg_alias (nbuf, old->number, old->type);
-
-  for (p = nbuf; *p; p++)
-    *p = TOUPPER (*p);
+  if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
+    {
+      for (p = nbuf; *p; p++)
+       *p = TOUPPER (*p);

 
 

-  if (strncmp (nbuf, newname, nlen))
-    insert_reg_alias (nbuf, old->number, old->type);
+      if (strncmp (nbuf, newname, nlen))
+       {
+         /* If this attempt to create an additional alias fails, do not bother
+            trying to create the all-lower case alias.  We will fail and issue
+            a second, duplicate error message.  This situation arises when the
+            programmer does something like:
+              foo .req r0
+              Foo .req r1
+            The second .req creates the "Foo" alias but then fails to create
+            the artifical FOO alias because it has already been created by the
+            first .req.  */
+         if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
+           return TRUE;
+       }

 
 

-  for (p = nbuf; *p; p++)
-    *p = TOLOWER (*p);
+      for (p = nbuf; *p; p++)
+       *p = TOLOWER (*p);

 
 

-  if (strncmp (nbuf, newname, nlen))
-    insert_reg_alias (nbuf, old->number, old->type);
+      if (strncmp (nbuf, newname, nlen))
+       insert_reg_alias (nbuf, old->number, old->type);
+    }

 
 

-  return 1;
+  return TRUE;

 }
 
 /* Create a Neon typed/indexed register alias using directives, e.g.:
 }
 
 /* Create a Neon typed/indexed register alias using directives, e.g.:


@@ -2267,11 +2283,45 @@ s_unreq (int a ATTRIBUTE_UNUSED)
                 name);
       else
        {
                 name);
       else
        {

+         char * p;
+         char * nbuf;
+

          hash_delete (arm_reg_hsh, name);
          free ((char *) reg->name);
           if (reg->neon)
             free (reg->neon);
          free (reg);
          hash_delete (arm_reg_hsh, name);
          free ((char *) reg->name);
           if (reg->neon)
             free (reg->neon);
          free (reg);

+
+         /* Also locate the all upper case and all lower case versions.
+            Do not complain if we cannot find one or the other as it
+            was probably deleted above.  */
+         
+         nbuf = strdup (name);
+         for (p = nbuf; *p; p++)
+           *p = TOUPPER (*p);
+         reg = hash_find (arm_reg_hsh, nbuf);
+         if (reg)
+           {
+             hash_delete (arm_reg_hsh, nbuf);
+             free ((char *) reg->name);
+             if (reg->neon)
+               free (reg->neon);
+             free (reg);
+           }
+
+         for (p = nbuf; *p; p++)
+           *p = TOLOWER (*p);
+         reg = hash_find (arm_reg_hsh, nbuf);
+         if (reg)
+           {
+             hash_delete (arm_reg_hsh, nbuf);
+             free ((char *) reg->name);
+             if (reg->neon)
+               free (reg->neon);
+             free (reg);
+           }
+
+         free (nbuf);

        }
     }
 
        }
     }
 


@@ -2610,6 +2660,7 @@ static void
 s_align (int unused ATTRIBUTE_UNUSED)
 {
   int temp;
 s_align (int unused ATTRIBUTE_UNUSED)
 {
   int temp;

+  bfd_boolean fill_p;

   long temp_fill;
   long max_alignment = 15;
 
   long temp_fill;
   long max_alignment = 15;
 


@@ -2626,16 +2677,25 @@ s_align (int unused ATTRIBUTE_UNUSED)
     {
       input_line_pointer++;
       temp_fill = get_absolute_expression ();
     {
       input_line_pointer++;
       temp_fill = get_absolute_expression ();

+      fill_p = TRUE;

     }
   else
     }
   else

-    temp_fill = 0;
+    {
+      fill_p = FALSE;
+      temp_fill = 0;
+    }

 
   if (!temp)
     temp = 2;
 
   /* Only make a frag if we HAVE to.  */
   if (temp && !need_pass_2)
 
   if (!temp)
     temp = 2;
 
   /* Only make a frag if we HAVE to.  */
   if (temp && !need_pass_2)

-    frag_align (temp, (int) temp_fill, 0);
+    {
+      if (!fill_p && subseg_text_p (now_seg))
+       frag_align_code (temp, 0);
+      else
+       frag_align (temp, (int) temp_fill, 0);
+    }

   demand_empty_rest_of_line ();
 
   record_alignment (now_seg, temp);
   demand_empty_rest_of_line ();
 
   record_alignment (now_seg, temp);


@@ -3816,84 +3876,7 @@ s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
 static void
 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
 {
 static void
 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
 {

-  expressionS exp;
-  bfd_boolean is_string;
-  int tag;
-  unsigned int i = 0;
-  char *s = NULL;
-  char saved_char;
-
-  expression (& exp);
-  if (exp.X_op != O_constant)
-    goto bad;
-
-  tag = exp.X_add_number;
-  if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0))
-    is_string = 1;
-  else
-    is_string = 0;
-
-  if (skip_past_comma (&input_line_pointer) == FAIL)
-    goto bad;
-  if (tag == 32 || !is_string)
-    {
-      expression (& exp);
-      if (exp.X_op != O_constant)
-       {
-         as_bad (_("expected numeric constant"));
-         ignore_rest_of_line ();
-         return;
-       }
-      i = exp.X_add_number;
-    }
-  if (tag == Tag_compatibility
-      && skip_past_comma (&input_line_pointer) == FAIL)
-    {
-      as_bad (_("expected comma"));
-      ignore_rest_of_line ();
-      return;
-    }
-  if (is_string)
-    {
-      skip_whitespace(input_line_pointer);
-      if (*input_line_pointer != '"')
-       goto bad_string;
-      input_line_pointer++;
-      s = input_line_pointer;
-      while (*input_line_pointer && *input_line_pointer != '"')
-       input_line_pointer++;
-      if (*input_line_pointer != '"')
-       goto bad_string;
-      saved_char = *input_line_pointer;
-      *input_line_pointer = 0;
-    }
-  else
-    {
-      s = NULL;
-      saved_char = 0;
-    }
-  
-  if (tag == Tag_compatibility)
-    elf32_arm_add_eabi_attr_compat (stdoutput, i, s);
-  else if (is_string)
-    elf32_arm_add_eabi_attr_string (stdoutput, tag, s);
-  else
-    elf32_arm_add_eabi_attr_int (stdoutput, tag, i);
-
-  if (s)
-    {
-      *input_line_pointer = saved_char;
-      input_line_pointer++;
-    }
-  demand_empty_rest_of_line ();
-  return;
-bad_string:
-  as_bad (_("bad string constant"));
-  ignore_rest_of_line ();
-  return;
-bad:
-  as_bad (_("expected <tag> , <value>"));
-  ignore_rest_of_line ();
+  s_vendor_attribute (OBJ_ATTR_PROC);

 }
 #endif /* OBJ_ELF */
 
 }
 #endif /* OBJ_ELF */
 


@@ -4177,18 +4160,43 @@ is_quarter_float (unsigned imm)
 
 /* Parse an 8-bit "quarter-precision" floating point number of the form:
    0baBbbbbbc defgh000 00000000 00000000.
 
 /* Parse an 8-bit "quarter-precision" floating point number of the form:
    0baBbbbbbc defgh000 00000000 00000000.

-   The minus-zero case needs special handling, since it can't be encoded in the
-   "quarter-precision" float format, but can nonetheless be loaded as an integer
-   constant.  */
+   The zero and minus-zero cases need special handling, since they can't be
+   encoded in the "quarter-precision" float format, but can nonetheless be
+   loaded as integer constants.  */

 
 static unsigned
 parse_qfloat_immediate (char **ccp, int *immed)
 {
   char *str = *ccp;
 
 static unsigned
 parse_qfloat_immediate (char **ccp, int *immed)
 {
   char *str = *ccp;

+  char *fpnum;

   LITTLENUM_TYPE words[MAX_LITTLENUMS];
   LITTLENUM_TYPE words[MAX_LITTLENUMS];

+  int found_fpchar = 0;

   
   skip_past_char (&str, '#');
   
   
   skip_past_char (&str, '#');
   

+  /* We must not accidentally parse an integer as a floating-point number. Make
+     sure that the value we parse is not an integer by checking for special
+     characters '.' or 'e'.
+     FIXME: This is a horrible hack, but doing better is tricky because type
+     information isn't in a very usable state at parse time.  */
+  fpnum = str;
+  skip_whitespace (fpnum);
+
+  if (strncmp (fpnum, "0x", 2) == 0)
+    return FAIL;
+  else
+    {
+      for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
+        if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
+          {
+            found_fpchar = 1;
+            break;
+          }
+
+      if (!found_fpchar)
+        return FAIL;
+    }
+  

   if ((str = atof_ieee (str, 's', words)) != NULL)
     {
       unsigned fpword = 0;
   if ((str = atof_ieee (str, 's', words)) != NULL)
     {
       unsigned fpword = 0;


@@ -4201,7 +4209,7 @@ parse_qfloat_immediate (char **ccp, int *immed)
           fpword |= words[i];
         }
       
           fpword |= words[i];
         }
       

-      if (is_quarter_float (fpword) || fpword == 0x80000000)
+      if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)

         *immed = fpword;
       else
         return FAIL;
         *immed = fpword;
       else
         return FAIL;


@@ -5201,7 +5209,7 @@ parse_neon_mov (char **str, int *which_operand)
              Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
              Case 10: VMOV.F32 <Sd>, #<imm>
              Case 11: VMOV.F64 <Dd>, #<imm>  */
              Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
              Case 10: VMOV.F32 <Sd>, #<imm>
              Case 11: VMOV.F64 <Dd>, #<imm>  */

-        ;
+        inst.operands[i].immisfloat = 1;

       else if (parse_big_immediate (&ptr, i) == SUCCESS)
           /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
              Case 3: VMOV<c><q>.<dt> <Dd>, #<imm>  */
       else if (parse_big_immediate (&ptr, i) == SUCCESS)
           /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
              Case 3: VMOV<c><q>.<dt> <Dd>, #<imm>  */


@@ -5452,6 +5460,7 @@ enum operand_parse_code
 
   OP_oRR,       /* ARM register */
   OP_oRRnpc,    /* ARM register, not the PC */
 
   OP_oRR,       /* ARM register */
   OP_oRRnpc,    /* ARM register, not the PC */

+  OP_oRRw,      /* ARM register, not r15, optional trailing ! */

   OP_oRND,       /* Optional Neon double precision register */
   OP_oRNQ,       /* Optional Neon quad precision register */
   OP_oRNDQ,      /* Optional Neon double or quad precision register */
   OP_oRND,       /* Optional Neon double precision register */
   OP_oRNQ,       /* Optional Neon quad precision register */
   OP_oRNDQ,      /* Optional Neon double or quad precision register */


@@ -5556,7 +5565,7 @@ parse_operands (char *str, const unsigned char *pattern)
          backtrack_index = i;
        }
 
          backtrack_index = i;
        }
 

-      if (i > 0)
+      if (i > 0 && (i > 1 || inst.operands[0].present))

        po_char_or_fail (',');
 
       switch (upat[i])
        po_char_or_fail (',');
 
       switch (upat[i])


@@ -5573,7 +5582,13 @@ parse_operands (char *str, const unsigned char *pattern)
        case OP_RVD:   po_reg_or_fail (REG_TYPE_VFD);     break;
         case OP_oRND:
        case OP_RND:   po_reg_or_fail (REG_TYPE_VFD);     break;
        case OP_RVD:   po_reg_or_fail (REG_TYPE_VFD);     break;
         case OP_oRND:
        case OP_RND:   po_reg_or_fail (REG_TYPE_VFD);     break;

-       case OP_RVC:   po_reg_or_fail (REG_TYPE_VFC);     break;
+       case OP_RVC:
+         po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
+         break;
+         /* Also accept generic coprocessor regs for unknown registers.  */
+         coproc_reg:
+         po_reg_or_fail (REG_TYPE_CN);
+         break;

        case OP_RMF:   po_reg_or_fail (REG_TYPE_MVF);     break;
        case OP_RMD:   po_reg_or_fail (REG_TYPE_MVD);     break;
        case OP_RMFX:  po_reg_or_fail (REG_TYPE_MVFX);    break;
        case OP_RMF:   po_reg_or_fail (REG_TYPE_MVF);     break;
        case OP_RMD:   po_reg_or_fail (REG_TYPE_MVD);     break;
        case OP_RMFX:  po_reg_or_fail (REG_TYPE_MVFX);    break;


@@ -5712,6 +5727,7 @@ parse_operands (char *str, const unsigned char *pattern)
          break;
 
        case OP_RRw:
          break;
 
        case OP_RRw:

+       case OP_oRRw:

          po_reg_or_fail (REG_TYPE_RN);
          if (skip_past_char (&str, '!') == SUCCESS)
            inst.operands[i].writeback = 1;
          po_reg_or_fail (REG_TYPE_RN);
          if (skip_past_char (&str, '!') == SUCCESS)
            inst.operands[i].writeback = 1;


@@ -5999,6 +6015,7 @@ parse_operands (char *str, const unsigned char *pattern)
        case OP_RRnpc:
        case OP_RRnpcb:
        case OP_RRw:
        case OP_RRnpc:
        case OP_RRnpcb:
        case OP_RRw:

+       case OP_oRRw:

        case OP_RRnpc_I0:
          if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
            inst.error = BAD_PC;
        case OP_RRnpc_I0:
          if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
            inst.error = BAD_PC;


@@ -7051,17 +7068,16 @@ do_lstc (void)
 static void
 do_mlas (void)
 {
 static void
 do_mlas (void)
 {

-  /* This restriction does not apply to mls (nor to mla in v6, but
-     that's hard to detect at present).         */
+  /* This restriction does not apply to mls (nor to mla in v6 or later).  */

   if (inst.operands[0].reg == inst.operands[1].reg
   if (inst.operands[0].reg == inst.operands[1].reg

+      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)

       && !(inst.instruction & 0x00400000))
       && !(inst.instruction & 0x00400000))

-    as_tsktsk (_("rd and rm should be different in mla"));
+    as_tsktsk (_("Rd and Rm should be different in mla"));

 
   inst.instruction |= inst.operands[0].reg << 16;
   inst.instruction |= inst.operands[1].reg;
   inst.instruction |= inst.operands[2].reg << 8;
   inst.instruction |= inst.operands[3].reg << 12;
 
   inst.instruction |= inst.operands[0].reg << 16;
   inst.instruction |= inst.operands[1].reg;
   inst.instruction |= inst.operands[2].reg << 8;
   inst.instruction |= inst.operands[3].reg << 12;

-

 }
 
 static void
 }
 
 static void


@@ -7169,8 +7185,9 @@ do_mul (void)
   inst.instruction |= inst.operands[1].reg;
   inst.instruction |= inst.operands[2].reg << 8;
 
   inst.instruction |= inst.operands[1].reg;
   inst.instruction |= inst.operands[2].reg << 8;
 

-  if (inst.operands[0].reg == inst.operands[1].reg)
-    as_tsktsk (_("rd and rm should be different in mul"));
+  if (inst.operands[0].reg == inst.operands[1].reg
+      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
+    as_tsktsk (_("Rd and Rm should be different in mul"));

 }
 
 /* Long Multiply Parser
 }
 
 /* Long Multiply Parser


@@ -7436,13 +7453,25 @@ do_smul (void)
   inst.instruction |= inst.operands[2].reg << 8;
 }
 
   inst.instruction |= inst.operands[2].reg << 8;
 }
 

-/* ARM V6 srs (argument parse).         */
+/* ARM V6 srs (argument parse).  The variable fields in the encoding are
+   the same for both ARM and Thumb-2.  */

 
 static void
 do_srs (void)
 {
 
 static void
 do_srs (void)
 {

-  inst.instruction |= inst.operands[0].imm;
-  if (inst.operands[0].writeback)
+  int reg;
+
+  if (inst.operands[0].present)
+    {
+      reg = inst.operands[0].reg;
+      constraint (reg != 13, _("SRS base register must be r13"));
+    }
+  else
+    reg = 13;
+
+  inst.instruction |= reg << 16;
+  inst.instruction |= inst.operands[1].imm;
+  if (inst.operands[0].writeback || inst.operands[1].writeback)

     inst.instruction |= WRITE_BACK;
 }
 
     inst.instruction |= WRITE_BACK;
 }
 


@@ -8244,7 +8273,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
   X(cpsie, b660, f3af8400),                    \
   X(cpsid, b670, f3af8600),                    \
   X(cpy,   4600, ea4f0000),                    \
   X(cpsie, b660, f3af8400),                    \
   X(cpsid, b670, f3af8600),                    \
   X(cpy,   4600, ea4f0000),                    \

-  X(dec_sp,80dd, f1bd0d00),                    \
+  X(dec_sp,80dd, f1ad0d00),                    \

   X(eor,   4040, ea800000),                    \
   X(eors,  4040, ea900000),                    \
   X(inc_sp,00dd, f10d0d00),                    \
   X(eor,   4040, ea800000),                    \
   X(eors,  4040, ea900000),                    \
   X(inc_sp,00dd, f10d0d00),                    \


@@ -8398,7 +8427,21 @@ do_t_add_sub (void)
          if (inst.size_req == 4
              || (inst.size_req != 2 && !opcode))
            {
          if (inst.size_req == 4
              || (inst.size_req != 2 && !opcode))
            {

-             if (Rs == REG_PC)
+             if (Rd == REG_PC)
+               {
+                 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
+                            _("only SUBS PC, LR, #const allowed"));
+                 constraint (inst.reloc.exp.X_op != O_constant,
+                             _("expression too complex"));
+                 constraint (inst.reloc.exp.X_add_number < 0
+                             || inst.reloc.exp.X_add_number > 0xff,
+                            _("immediate value out of range"));
+                 inst.instruction = T2_SUBS_PC_LR
+                                    | inst.reloc.exp.X_add_number;
+                 inst.reloc.type = BFD_RELOC_UNUSED;
+                 return;
+               }
+             else if (Rs == REG_PC)

                {
                  /* Always use addw/subw.  */
                  inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
                {
                  /* Always use addw/subw.  */
                  inst.instruction = add ? 0xf20f0000 : 0xf2af0000;


@@ -8414,8 +8457,8 @@ do_t_add_sub (void)
                  else
                    inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
                }
                  else
                    inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
                }

-             inst.instruction |= inst.operands[0].reg << 8;
-             inst.instruction |= inst.operands[1].reg << 16;
+             inst.instruction |= Rd << 8;
+             inst.instruction |= Rs << 16;

            }
        }
       else
            }
        }
       else


@@ -9045,6 +9088,68 @@ do_t_it (void)
   inst.instruction |= cond << 4;
 }
 
   inst.instruction |= cond << 4;
 }
 

+/* Helper function used for both push/pop and ldm/stm.  */
+static void
+encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
+{
+  bfd_boolean load;
+
+  load = (inst.instruction & (1 << 20)) != 0;
+
+  if (mask & (1 << 13))
+    inst.error =  _("SP not allowed in register list");
+  if (load)
+    {
+      if (mask & (1 << 14)
+         && mask & (1 << 15))
+       inst.error = _("LR and PC should not both be in register list");
+
+      if ((mask & (1 << base)) != 0
+         && writeback)
+       as_warn (_("base register should not be in register list "
+                  "when written back"));
+    }
+  else
+    {
+      if (mask & (1 << 15))
+       inst.error = _("PC not allowed in register list");
+
+      if (mask & (1 << base))
+       as_warn (_("value stored for r%d is UNPREDICTABLE"), base);
+    }
+
+  if ((mask & (mask - 1)) == 0)
+    {
+      /* Single register transfers implemented as str/ldr.  */
+      if (writeback)
+       {
+         if (inst.instruction & (1 << 23))
+           inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
+         else
+           inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
+       }
+      else
+       {
+         if (inst.instruction & (1 << 23))
+           inst.instruction = 0x00800000; /* ia -> [base] */
+         else
+           inst.instruction = 0x00000c04; /* db -> [base, #-4] */
+       }
+
+      inst.instruction |= 0xf8400000;
+      if (load)
+       inst.instruction |= 0x00100000;
+
+      mask = ffs(mask) - 1;
+      mask <<= 12;
+    }
+  else if (writeback)
+    inst.instruction |= WRITE_BACK;
+
+  inst.instruction |= mask;
+  inst.instruction |= base << 16;
+}
+

 static void
 do_t_ldmstm (void)
 {
 static void
 do_t_ldmstm (void)
 {


@@ -9056,60 +9161,60 @@ do_t_ldmstm (void)
 
   if (unified_syntax)
     {
 
   if (unified_syntax)
     {

+      bfd_boolean narrow;
+      unsigned mask;
+
+      narrow = FALSE;

       /* See if we can use a 16-bit instruction.  */
       if (inst.instruction < 0xffff /* not ldmdb/stmdb */
          && inst.size_req != 4
       /* See if we can use a 16-bit instruction.  */
       if (inst.instruction < 0xffff /* not ldmdb/stmdb */
          && inst.size_req != 4

-         && inst.operands[0].reg <= 7
-         && !(inst.operands[1].imm & ~0xff)
-         && (inst.instruction == T_MNEM_stmia
-             ? inst.operands[0].writeback
-             : (inst.operands[0].writeback
-                == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
+         && !(inst.operands[1].imm & ~0xff))

        {
        {

-         if (inst.instruction == T_MNEM_stmia
-             && (inst.operands[1].imm & (1 << inst.operands[0].reg))
-             && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
-           as_warn (_("value stored for r%d is UNPREDICTABLE"),
-                    inst.operands[0].reg);
+         mask = 1 << inst.operands[0].reg;

 
 

-         inst.instruction = THUMB_OP16 (inst.instruction);
-         inst.instruction |= inst.operands[0].reg << 8;
-         inst.instruction |= inst.operands[1].imm;
-       }
-      else
-       {
-         if (inst.operands[1].imm & (1 << 13))
-           as_warn (_("SP should not be in register list"));
-         if (inst.instruction == T_MNEM_stmia)
+         if (inst.operands[0].reg <= 7
+             && (inst.instruction == T_MNEM_stmia
+                 ? inst.operands[0].writeback
+                 : (inst.operands[0].writeback
+                    == !(inst.operands[1].imm & mask))))

            {
            {

-             if (inst.operands[1].imm & (1 << 15))
-               as_warn (_("PC should not be in register list"));
-             if (inst.operands[1].imm & (1 << inst.operands[0].reg))
+             if (inst.instruction == T_MNEM_stmia
+                 && (inst.operands[1].imm & mask)
+                 && (inst.operands[1].imm & (mask - 1)))

                as_warn (_("value stored for r%d is UNPREDICTABLE"),
                         inst.operands[0].reg);
                as_warn (_("value stored for r%d is UNPREDICTABLE"),
                         inst.operands[0].reg);

+
+             inst.instruction = THUMB_OP16 (inst.instruction);
+             inst.instruction |= inst.operands[0].reg << 8;
+             inst.instruction |= inst.operands[1].imm;
+             narrow = TRUE;

            }
            }

-         else
+         else if (inst.operands[0] .reg == REG_SP
+                  && inst.operands[0].writeback)

            {
            {

-             if (inst.operands[1].imm & (1 << 14)
-                 && inst.operands[1].imm & (1 << 15))
-               as_warn (_("LR and PC should not both be in register list"));
-             if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
-                 && inst.operands[0].writeback)
-               as_warn (_("base register should not be in register list "
-                          "when written back"));
+             inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia
+                                            ? T_MNEM_push : T_MNEM_pop);
+             inst.instruction |= inst.operands[1].imm;
+             narrow = TRUE;

            }
            }

+       }
+
+      if (!narrow)
+       {

          if (inst.instruction < 0xffff)
            inst.instruction = THUMB_OP32 (inst.instruction);
          if (inst.instruction < 0xffff)
            inst.instruction = THUMB_OP32 (inst.instruction);

-         inst.instruction |= inst.operands[0].reg << 16;
-         inst.instruction |= inst.operands[1].imm;
-         if (inst.operands[0].writeback)
-           inst.instruction |= WRITE_BACK;
+
+         encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm,
+                              inst.operands[0].writeback);

        }
     }
   else
     {
       constraint (inst.operands[0].reg > 7
                  || (inst.operands[1].imm & ~0xff), BAD_HIREG);
        }
     }
   else
     {
       constraint (inst.operands[0].reg > 7
                  || (inst.operands[1].imm & ~0xff), BAD_HIREG);

+      constraint (inst.instruction != T_MNEM_ldmia
+                 && inst.instruction != T_MNEM_stmia,
+                 _("Thumb-2 instruction only valid in unified syntax"));

       if (inst.instruction == T_MNEM_stmia)
        {
          if (!inst.operands[0].writeback)
       if (inst.instruction == T_MNEM_stmia)
        {
          if (!inst.operands[0].writeback)


@@ -9383,6 +9488,16 @@ do_t_mov_cmp (void)
          || inst.operands[1].shifted)
        narrow = FALSE;
 
          || inst.operands[1].shifted)
        narrow = FALSE;
 

+      /* MOVS PC, LR is encoded as SUBS PC, LR, #0.  */
+      if (opcode == T_MNEM_movs && inst.operands[1].isreg
+         && !inst.operands[1].shifted
+         && inst.operands[0].reg == REG_PC
+         && inst.operands[1].reg == REG_LR)
+       {
+         inst.instruction = T2_SUBS_PC_LR;
+         return;
+       }
+

       if (!inst.operands[1].isreg)
        {
          /* Immediate operand.  */
       if (!inst.operands[1].isreg)
        {
          /* Immediate operand.  */


@@ -9405,11 +9520,98 @@ do_t_mov_cmp (void)
              inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
            }
        }
              inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
            }
        }

+      else if (inst.operands[1].shifted && inst.operands[1].immisreg
+              && (inst.instruction == T_MNEM_mov
+                  || inst.instruction == T_MNEM_movs))
+       {
+         /* Register shifts are encoded as separate shift instructions.  */
+         bfd_boolean flags = (inst.instruction == T_MNEM_movs);
+
+         if (current_it_mask)
+           narrow = !flags;
+         else
+           narrow = flags;
+
+         if (inst.size_req == 4)
+           narrow = FALSE;
+
+         if (!low_regs || inst.operands[1].imm > 7)
+           narrow = FALSE;
+
+         if (inst.operands[0].reg != inst.operands[1].reg)
+           narrow = FALSE;
+
+         switch (inst.operands[1].shift_kind)
+           {
+           case SHIFT_LSL:
+             opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
+             break;
+           case SHIFT_ASR:
+             opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
+             break;
+           case SHIFT_LSR:
+             opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
+             break;
+           case SHIFT_ROR:
+             opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
+             break;
+           default:
+             abort();
+           }
+
+         inst.instruction = opcode;
+         if (narrow)
+           {
+             inst.instruction |= inst.operands[0].reg;
+             inst.instruction |= inst.operands[1].imm << 3;
+           }
+         else
+           {
+             if (flags)
+               inst.instruction |= CONDS_BIT;
+
+             inst.instruction |= inst.operands[0].reg << 8;
+             inst.instruction |= inst.operands[1].reg << 16;
+             inst.instruction |= inst.operands[1].imm;
+           }
+       }

       else if (!narrow)
        {
       else if (!narrow)
        {

-         inst.instruction = THUMB_OP32 (inst.instruction);
-         inst.instruction |= inst.operands[0].reg << r0off;
-         encode_thumb32_shifted_operand (1);
+         /* Some mov with immediate shift have narrow variants.
+            Register shifts are handled above.  */
+         if (low_regs && inst.operands[1].shifted
+             && (inst.instruction == T_MNEM_mov
+                 || inst.instruction == T_MNEM_movs))
+           {
+             if (current_it_mask)
+               narrow = (inst.instruction == T_MNEM_mov);
+             else
+               narrow = (inst.instruction == T_MNEM_movs);
+           }
+
+         if (narrow)
+           {
+             switch (inst.operands[1].shift_kind)
+               {
+               case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
+               case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
+               case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
+               default: narrow = FALSE; break;
+               }
+           }
+
+         if (narrow)
+           {
+             inst.instruction |= inst.operands[0].reg;
+             inst.instruction |= inst.operands[1].reg << 3;
+             inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
+           }
+         else
+           {
+             inst.instruction = THUMB_OP32 (inst.instruction);
+             inst.instruction |= inst.operands[0].reg << r0off;
+             encode_thumb32_shifted_operand (1);
+           }

        }
       else
        switch (inst.instruction)
        }
       else
        switch (inst.instruction)


@@ -9789,7 +9991,7 @@ do_t_push_pop (void)
 
   mask = inst.operands[0].imm;
   if ((mask & ~0xff) == 0)
 
   mask = inst.operands[0].imm;
   if ((mask & ~0xff) == 0)

-    inst.instruction = THUMB_OP16 (inst.instruction);
+    inst.instruction = THUMB_OP16 (inst.instruction) | mask;

   else if ((inst.instruction == T_MNEM_push
            && (mask & ~0xff) == 1 << REG_LR)
           || (inst.instruction == T_MNEM_pop
   else if ((inst.instruction == T_MNEM_push
            && (mask & ~0xff) == 1 << REG_LR)
           || (inst.instruction == T_MNEM_pop


@@ -9797,43 +9999,18 @@ do_t_push_pop (void)
     {
       inst.instruction = THUMB_OP16 (inst.instruction);
       inst.instruction |= THUMB_PP_PC_LR;
     {
       inst.instruction = THUMB_OP16 (inst.instruction);
       inst.instruction |= THUMB_PP_PC_LR;

-      mask &= 0xff;
+      inst.instruction |= mask & 0xff;

     }
   else if (unified_syntax)
     {
     }
   else if (unified_syntax)
     {

-      if (mask & (1 << 13))
-       inst.error =  _("SP not allowed in register list");
-      if (inst.instruction == T_MNEM_push)
-       {
-         if (mask & (1 << 15))
-           inst.error = _("PC not allowed in register list");
-       }
-      else
-       {
-         if (mask & (1 << 14)
-             && mask & (1 << 15))
-           inst.error = _("LR and PC should not both be in register list");
-       }
-      if ((mask & (mask - 1)) == 0)
-       {
-         /* Single register push/pop implemented as str/ldr.  */
-         if (inst.instruction == T_MNEM_push)
-           inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
-         else
-           inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
-         mask = ffs(mask) - 1;
-         mask <<= 12;
-       }
-      else
-       inst.instruction = THUMB_OP32 (inst.instruction);
+      inst.instruction = THUMB_OP32 (inst.instruction);
+      encode_thumb2_ldmstm(13, mask, TRUE);

     }
   else
     {
       inst.error = _("invalid register list to push/pop instruction");
       return;
     }
     }
   else
     {
       inst.error = _("invalid register list to push/pop instruction");
       return;
     }

-
-  inst.instruction |= mask;

 }
 
 static void
 }
 
 static void


@@ -9878,8 +10055,37 @@ do_t_rsb (void)
   inst.instruction |= Rs << 16;
   if (!inst.operands[2].isreg)
     {
   inst.instruction |= Rs << 16;
   if (!inst.operands[2].isreg)
     {

-      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
-      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+      bfd_boolean narrow;
+
+      if ((inst.instruction & 0x00100000) != 0)
+       narrow = (current_it_mask == 0);
+      else
+       narrow = (current_it_mask != 0);
+
+      if (Rd > 7 || Rs > 7)
+       narrow = FALSE;
+
+      if (inst.size_req == 4 || !unified_syntax)
+       narrow = FALSE;
+
+      if (inst.reloc.exp.X_op != O_constant
+         || inst.reloc.exp.X_add_number != 0)
+       narrow = FALSE;
+
+      /* Turn rsb #0 into 16-bit neg.  We should probably do this via
+         relaxation, but it doesn't seem worth the hassle.  */
+      if (narrow)
+       {
+         inst.reloc.type = BFD_RELOC_UNUSED;
+         inst.instruction = THUMB_OP16 (T_MNEM_negs);
+         inst.instruction |= Rs << 3;
+         inst.instruction |= Rd;
+       }
+      else
+       {
+         inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+         inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+       }

     }
   else
     encode_thumb32_shifted_operand (2);
     }
   else
     encode_thumb32_shifted_operand (2);


@@ -11257,9 +11463,9 @@ do_vfp_nsyn_pop (void)
 {
   nsyn_insert_sp ();
   if (inst.operands[1].issingle)
 {
   nsyn_insert_sp ();
   if (inst.operands[1].issingle)

-    do_vfp_nsyn_opcode ("fldmdbs");
+    do_vfp_nsyn_opcode ("fldmias");

   else
   else

-    do_vfp_nsyn_opcode ("fldmdbd");
+    do_vfp_nsyn_opcode ("fldmiad");

 }
 
 /* Fix up Neon data-processing instructions, ORing in the correct bits for
 }
 
 /* Fix up Neon data-processing instructions, ORing in the correct bits for


@@ -11550,9 +11756,15 @@ neon_qfloat_bits (unsigned imm)
    try smaller element sizes.  */
 
 static int
    try smaller element sizes.  */
 
 static int

-neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, unsigned *immbits,
-                         int *op, int size, enum neon_el_type type)
+neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
+                        unsigned *immbits, int *op, int size,
+                        enum neon_el_type type)

 {
 {

+  /* Only permit float immediates (including 0.0/-0.0) if the operand type is
+     float.  */
+  if (type == NT_float && !float_p)
+    return FAIL;
+

   if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
     {
       if (size != 32 || *op == 1)
   if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
     {
       if (size != 32 || *op == 1)


@@ -12548,7 +12760,7 @@ neon_move_immediate (void)
   struct neon_type_el et = neon_check_type (2, rs,
     N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
   unsigned immlo, immhi = 0, immbits;
   struct neon_type_el et = neon_check_type (2, rs,
     N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
   unsigned immlo, immhi = 0, immbits;

-  int op, cmode;
+  int op, cmode, float_p;

 
   constraint (et.type == NT_invtype,
               _("operand size must be specified for immediate VMOV"));
 
   constraint (et.type == NT_invtype,
               _("operand size must be specified for immediate VMOV"));


@@ -12563,7 +12775,9 @@ neon_move_immediate (void)
   constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
               _("immediate has bits set outside the operand size"));
 
   constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
               _("immediate has bits set outside the operand size"));
 

-  if ((cmode = neon_cmode_for_move_imm (immlo, immhi, &immbits, &op,
+  float_p = inst.operands[1].immisfloat;
+
+  if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,

                                         et.size, et.type)) == FAIL)
     {
       /* Invert relevant bits only.  */
                                         et.size, et.type)) == FAIL)
     {
       /* Invert relevant bits only.  */


@@ -12572,8 +12786,8 @@ neon_move_immediate (void)
          with one or the other; those cases are caught by
          neon_cmode_for_move_imm.  */
       op = !op;
          with one or the other; those cases are caught by
          neon_cmode_for_move_imm.  */
       op = !op;

-      if ((cmode = neon_cmode_for_move_imm (immlo, immhi, &immbits, &op,
-                                            et.size, et.type)) == FAIL)
+      if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
+                                           &op, et.size, et.type)) == FAIL)

         {
           first_error (_("immediate out of range"));
           return;
         {
           first_error (_("immediate out of range"));
           return;


@@ -12729,6 +12943,7 @@ do_neon_ext (void)
   struct neon_type_el et = neon_check_type (3, rs,
     N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
   unsigned imm = (inst.operands[3].imm * et.size) / 8;
   struct neon_type_el et = neon_check_type (3, rs,
     N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
   unsigned imm = (inst.operands[3].imm * et.size) / 8;

+  constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range"));

   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
   inst.instruction |= HI1 (inst.operands[0].reg) << 22;
   inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
   inst.instruction |= HI1 (inst.operands[0].reg) << 22;
   inst.instruction |= LOW4 (inst.operands[1].reg) << 16;


@@ -13994,6 +14209,14 @@ md_assemble (char *str)
          return;
        }
 
          return;
        }
 

+      if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
+       {
+         /* Implicit require narrow instructions on Thumb-1.  This avoids
+            relaxation accidentally introducing Thumb-2 instructions.  */
+         if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23)
+           inst.size_req = 2;
+       }
+

       /* Check conditional suffixes.  */
       if (current_it_mask)
        {
       /* Check conditional suffixes.  */
       if (current_it_mask)
        {


@@ -14035,6 +14258,11 @@ md_assemble (char *str)
              return;
            }
        }
              return;
            }
        }

+
+      /* Something has gone badly wrong if we try to relax a fixed size
+         instruction.  */
+      assert (inst.size_req == 0 || !inst.relax);
+

       ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
                              *opcode->tvariant);
       /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
       ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
                              *opcode->tvariant);
       /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly


@@ -14254,6 +14482,10 @@ static const struct reg_entry reg_names[] =
   /* VFP control registers.  */
   REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
   REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
   /* VFP control registers.  */
   REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
   REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),

+  REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
+  REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
+  REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
+  REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),

 
   /* Maverick DSP coprocessor registers.  */
   REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),
 
   /* Maverick DSP coprocessor registers.  */
   REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),


@@ -14370,20 +14602,21 @@ static const struct asm_psr psrs[] =
 /* Table of V7M psr names.  */
 static const struct asm_psr v7m_psrs[] =
 {
 /* Table of V7M psr names.  */
 static const struct asm_psr v7m_psrs[] =
 {

-  {"apsr",     0 },
-  {"iapsr",    1 },
-  {"eapsr",    2 },
-  {"psr",      3 },
-  {"ipsr",     5 },
-  {"epsr",     6 },
-  {"iepsr",    7 },
-  {"msp",      8 },
-  {"psp",      9 },
-  {"primask",  16},
-  {"basepri",  17},
-  {"basepri_max", 18},
-  {"faultmask",        19},
-  {"control",  20}
+  {"apsr",       0 }, {"APSR",         0 },
+  {"iapsr",      1 }, {"IAPSR",        1 },
+  {"eapsr",      2 }, {"EAPSR",        2 },
+  {"psr",        3 }, {"PSR",          3 },
+  {"xpsr",       3 }, {"XPSR",         3 }, {"xPSR",     3 },
+  {"ipsr",       5 }, {"IPSR",         5 },
+  {"epsr",       6 }, {"EPSR",         6 },
+  {"iepsr",      7 }, {"IEPSR",        7 },
+  {"msp",        8 }, {"MSP",          8 },
+  {"psp",        9 }, {"PSP",          9 },
+  {"primask",    16}, {"PRIMASK",      16},
+  {"basepri",    17}, {"BASEPRI",      17},
+  {"basepri_max", 18}, {"BASEPRI_MAX", 18},
+  {"faultmask",          19}, {"FAULTMASK",    19},
+  {"control",    20}, {"CONTROL",      20}

 };
 
 /* Table of all shift-in-operand names.         */
 };
 
 /* Table of all shift-in-operand names.         */


@@ -14711,6 +14944,10 @@ static const struct asm_opcode insns[] =
  tCE(push,     92d0000, push,     1, (REGLST),      push_pop, t_push_pop),
  tCE(pop,      8bd0000, pop,      1, (REGLST),      push_pop, t_push_pop),
 
  tCE(push,     92d0000, push,     1, (REGLST),      push_pop, t_push_pop),
  tCE(pop,      8bd0000, pop,      1, (REGLST),      push_pop, t_push_pop),
 

+ /* These may simplify to neg.  */
+ TCE(rsb,      0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
+ TC3(rsbs,     0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
+

 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6
  TCE(cpy,       1a00000, 4600,     2, (RR, RR),      rd_rm, t_cpy),
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6
  TCE(cpy,       1a00000, 4600,     2, (RR, RR),      rd_rm, t_cpy),


@@ -14718,8 +14955,6 @@ static const struct asm_opcode insns[] =
  /* V1 instructions with no Thumb analogue prior to V6T2.  */
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6t2
  /* V1 instructions with no Thumb analogue prior to V6T2.  */
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6t2

- TCE(rsb,      0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
- TC3(rsbs,     0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),

  TCE(teq,      1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
  TC3w(teqs,    1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
   CL(teqp,     130f000,           2, (RR, SH),      cmp),
  TCE(teq,      1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
  TC3w(teqs,    1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
   CL(teqp,     130f000,           2, (RR, SH),      cmp),


@@ -14859,8 +15094,8 @@ static const struct asm_opcode insns[] =
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v5e /*  ARM Architecture 5TE.  */
  TUF(pld,      450f000, f810f000, 1, (ADDR),                pld,  t_pld),
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v5e /*  ARM Architecture 5TE.  */
  TUF(pld,      450f000, f810f000, 1, (ADDR),                pld,  t_pld),

- TC3(ldrd,     00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
- TC3(strd,     00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
+ TC3(ldrd,     00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
+ TC3(strd,     00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),

 
  TCE(mcrr,     c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
  TCE(mrrc,     c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
 
  TCE(mcrr,     c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
  TCE(mrrc,     c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),


@@ -14887,6 +15122,7 @@ static const struct asm_opcode insns[] =
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6t2
  TCE(ldrex,    1900f9f, e8500f00, 2, (RRnpc, ADDR),              ldrex, t_ldrex),
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6t2
  TCE(ldrex,    1900f9f, e8500f00, 2, (RRnpc, ADDR),              ldrex, t_ldrex),

+ TCE(strex,    1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR),        strex,  t_strex),

  TUF(mcrr2,    c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
  TUF(mrrc2,    c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
 
  TUF(mcrr2,    c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
  TUF(mrrc2,    c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
 


@@ -14970,12 +15206,11 @@ static const struct asm_opcode insns[] =
  TCE(smuadx,   700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc),       smul, t_simd),
  TCE(smusd,    700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc),       smul, t_simd),
  TCE(smusdx,   700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc),       smul, t_simd),
  TCE(smuadx,   700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc),       smul, t_simd),
  TCE(smusd,    700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc),       smul, t_simd),
  TCE(smusdx,   700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc),       smul, t_simd),

- TUF(srsia,    8cd0500, e980c000, 1, (I31w),                      srs,  srs),
-  UF(srsib,    9cd0500,           1, (I31w),                      srs),
-  UF(srsda,    84d0500,           1, (I31w),                      srs),
- TUF(srsdb,    94d0500, e800c000, 1, (I31w),                      srs,  srs),
+ TUF(srsia,    8c00500, e980c000, 2, (oRRw, I31w),                srs,  srs),
+  UF(srsib,    9c00500,           2, (oRRw, I31w),                srs),
+  UF(srsda,    8400500,           2, (oRRw, I31w),                srs),
+ TUF(srsdb,    9400500, e800c000, 2, (oRRw, I31w),                srs,  srs),

  TCE(ssat16,   6a00f30, f3200000, 3, (RRnpc, I16, RRnpc),         ssat16, t_ssat16),
  TCE(ssat16,   6a00f30, f3200000, 3, (RRnpc, I16, RRnpc),         ssat16, t_ssat16),

- TCE(strex,    1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR),        strex,  t_strex),

  TCE(umaal,    0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,  t_mlal),
  TCE(usad8,    780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc),       smul,   t_simd),
  TCE(usada8,   7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla,   t_mla),
  TCE(umaal,    0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,  t_mlal),
  TCE(usad8,    780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc),       smul,   t_simd),
  TCE(usada8,   7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla,   t_mla),


@@ -15841,8 +16076,8 @@ static const struct asm_opcode insns[] =
  nUF(vmull,     vmull,   3, (RNQ, RND, RND_RNSC), neon_vmull),
 
   /* Extract. Size 8.  */
  nUF(vmull,     vmull,   3, (RNQ, RND, RND_RNSC), neon_vmull),
 
   /* Extract. Size 8.  */

- NUF(vext,      0b00000, 4, (RNDQ, oRNDQ, RNDQ, I7), neon_ext),
- NUF(vextq,     0b00000, 4, (RNQ,  oRNQ,  RNQ,  I7), neon_ext),
+ NUF(vext,      0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
+ NUF(vextq,     0b00000, 4, (RNQ,  oRNQ,  RNQ,  I15), neon_ext),

 
   /* Two registers, miscellaneous.  */
   /* Reverse. Sizes 8 16 32 (must be < size in opcode).  */
 
   /* Two registers, miscellaneous.  */
   /* Reverse. Sizes 8 16 32 (must be < size in opcode).  */


@@ -16525,16 +16760,66 @@ relax_immediate (fragS *fragp, int size, int shift)
   offset = fragp->fr_offset;
   /* Force misaligned offsets to 32-bit variant.  */
   if (offset & low)
   offset = fragp->fr_offset;
   /* Force misaligned offsets to 32-bit variant.  */
   if (offset & low)

-    return -4;
+    return 4;

   if (offset & ~mask)
     return 4;
   return 2;
 }
 
   if (offset & ~mask)
     return 4;
   return 2;
 }
 

+/* Get the address of a symbol during relaxation.  */
+static addressT
+relaxed_symbol_addr(fragS *fragp, long stretch)
+{
+  fragS *sym_frag;
+  addressT addr;
+  symbolS *sym;
+
+  sym = fragp->fr_symbol;
+  sym_frag = symbol_get_frag (sym);
+  know (S_GET_SEGMENT (sym) != absolute_section
+       || sym_frag == &zero_address_frag);
+  addr = S_GET_VALUE (sym) + fragp->fr_offset;
+
+  /* If frag has yet to be reached on this pass, assume it will
+     move by STRETCH just as we did.  If this is not so, it will
+     be because some frag between grows, and that will force
+     another pass.  */
+
+  if (stretch != 0
+      && sym_frag->relax_marker != fragp->relax_marker)
+    {
+      fragS *f;
+
+      /* Adjust stretch for any alignment frag.  Note that if have
+        been expanding the earlier code, the symbol may be
+        defined in what appears to be an earlier frag.  FIXME:
+        This doesn't handle the fr_subtype field, which specifies
+        a maximum number of bytes to skip when doing an
+        alignment.  */
+      for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
+       {
+         if (f->fr_type == rs_align || f->fr_type == rs_align_code)
+           {
+             if (stretch < 0)
+               stretch = - ((- stretch)
+                            & ~ ((1 << (int) f->fr_offset) - 1));
+             else
+               stretch &= ~ ((1 << (int) f->fr_offset) - 1);
+             if (stretch == 0)
+               break;
+           }
+       }
+      if (f != NULL)
+       addr += stretch;
+    }
+
+  return addr;
+}
+

 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
    load.  */
 static int
 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
    load.  */
 static int

-relax_adr (fragS *fragp, asection *sec)
+relax_adr (fragS *fragp, asection *sec, long stretch)

 {
   addressT addr;
   offsetT val;
 {
   addressT addr;
   offsetT val;


@@ -16544,14 +16829,12 @@ relax_adr (fragS *fragp, asection *sec)
       || sec != S_GET_SEGMENT (fragp->fr_symbol))
     return 4;
 
       || sec != S_GET_SEGMENT (fragp->fr_symbol))
     return 4;
 

-  val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
+  val = relaxed_symbol_addr(fragp, stretch);

   addr = fragp->fr_address + fragp->fr_fix;
   addr = (addr + 4) & ~3;
   addr = fragp->fr_address + fragp->fr_fix;
   addr = (addr + 4) & ~3;

-  /* Fix the insn as the 4-byte version if the target address is not
-     sufficiently aligned.  This is prevents an infinite loop when two
-     instructions have contradictory range/alignment requirements.  */
+  /* Force misaligned targets to 32-bit variant.  */

   if (val & 3)
   if (val & 3)

-    return -4;
+    return 4;

   val -= addr;
   if (val < 0 || val > 1020)
     return 4;
   val -= addr;
   if (val < 0 || val > 1020)
     return 4;


@@ -16578,7 +16861,7 @@ relax_addsub (fragS *fragp, asection *sec)
    size of the offset field in the narrow instruction.  */
 
 static int
    size of the offset field in the narrow instruction.  */
 
 static int

-relax_branch (fragS *fragp, asection *sec, int bits)
+relax_branch (fragS *fragp, asection *sec, int bits, long stretch)

 {
   addressT addr;
   offsetT val;
 {
   addressT addr;
   offsetT val;


@@ -16589,7 +16872,7 @@ relax_branch (fragS *fragp, asection *sec, int bits)
       || sec != S_GET_SEGMENT (fragp->fr_symbol))
     return 4;
 
       || sec != S_GET_SEGMENT (fragp->fr_symbol))
     return 4;
 

-  val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
+  val = relaxed_symbol_addr(fragp, stretch);

   addr = fragp->fr_address + fragp->fr_fix + 4;
   val -= addr;
 
   addr = fragp->fr_address + fragp->fr_fix + 4;
   val -= addr;
 


@@ -16605,7 +16888,7 @@ relax_branch (fragS *fragp, asection *sec, int bits)
    the current size of the frag should change.  */
 
 int
    the current size of the frag should change.  */
 
 int

-arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
+arm_relax_frag (asection *sec, fragS *fragp, long stretch)

 {
   int oldsize;
   int newsize;
 {
   int oldsize;
   int newsize;


@@ -16614,7 +16897,7 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
   switch (fragp->fr_subtype)
     {
     case T_MNEM_ldr_pc2:
   switch (fragp->fr_subtype)
     {
     case T_MNEM_ldr_pc2:

-      newsize = relax_adr(fragp, sec);
+      newsize = relax_adr(fragp, sec, stretch);

       break;
     case T_MNEM_ldr_pc:
     case T_MNEM_ldr_sp:
       break;
     case T_MNEM_ldr_pc:
     case T_MNEM_ldr_sp:


@@ -16634,7 +16917,7 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
       newsize = relax_immediate(fragp, 5, 0);
       break;
     case T_MNEM_adr:
       newsize = relax_immediate(fragp, 5, 0);
       break;
     case T_MNEM_adr:

-      newsize = relax_adr(fragp, sec);
+      newsize = relax_adr(fragp, sec, stretch);

       break;
     case T_MNEM_mov:
     case T_MNEM_movs:
       break;
     case T_MNEM_mov:
     case T_MNEM_movs:


@@ -16643,10 +16926,10 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
       newsize = relax_immediate(fragp, 8, 0);
       break;
     case T_MNEM_b:
       newsize = relax_immediate(fragp, 8, 0);
       break;
     case T_MNEM_b:

-      newsize = relax_branch(fragp, sec, 11);
+      newsize = relax_branch(fragp, sec, 11, stretch);

       break;
     case T_MNEM_bcond:
       break;
     case T_MNEM_bcond:

-      newsize = relax_branch(fragp, sec, 8);
+      newsize = relax_branch(fragp, sec, 8, stretch);

       break;
     case T_MNEM_add_sp:
     case T_MNEM_add_pc:
       break;
     case T_MNEM_add_sp:
     case T_MNEM_add_pc:


@@ -16665,14 +16948,18 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
     default:
       abort();
     }
     default:
       abort();
     }

-  if (newsize < 0)
+
+  fragp->fr_var = newsize;
+  /* Freeze wide instructions that are at or before the same location as
+     in the previous pass.  This avoids infinite loops.
+     Don't freeze them unconditionally because targets may be artificialy
+     misaligned by the expansion of preceeding frags.  */
+  if (stretch <= 0 && newsize > 2)

     {
     {

-      fragp->fr_var = -newsize;

       md_convert_frag (sec->owner, sec, fragp);
       frag_wane(fragp);
       md_convert_frag (sec->owner, sec, fragp);
       frag_wane(fragp);

-      return -(newsize + oldsize);

     }
     }

-  fragp->fr_var = newsize;
+

   return newsize - oldsize;
 }
 
   return newsize - oldsize;
 }
 


@@ -17763,7 +18050,7 @@ md_apply_fix (fixS *    fixP,
            as_bad_where (fixP->fx_file, fixP->fx_line,
                          _("invalid literal constant: pool needs to be closer"));
          else
            as_bad_where (fixP->fx_file, fixP->fx_line,
                          _("invalid literal constant: pool needs to be closer"));
          else

-           as_bad (_("bad immediate value for half-word offset (%ld)"),
+           as_bad (_("bad immediate value for 8-bit offset (%ld)"),

                    (long) value);
          break;
        }
                    (long) value);
          break;
        }


@@ -18073,16 +18360,32 @@ md_apply_fix (fixS *  fixP,
 
     case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
       /* CBZ can only branch forward.  */
 
     case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
       /* CBZ can only branch forward.  */

-      if (value & ~0x7e)
-       as_bad_where (fixP->fx_file, fixP->fx_line,
-                     _("branch out of range"));

 
 

-      if (fixP->fx_done || !seg->use_rela_p)
+      /* Attempts to use CBZ to branch to the next instruction
+         (which, strictly speaking, are prohibited) will be turned into
+         no-ops.
+
+        FIXME: It may be better to remove the instruction completely and
+        perform relaxation.  */
+      if (value == -2)

        {
          newval = md_chars_to_number (buf, THUMB_SIZE);
        {
          newval = md_chars_to_number (buf, THUMB_SIZE);

-         newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
+         newval = 0xbf00; /* NOP encoding T1 */

          md_number_to_chars (buf, newval, THUMB_SIZE);
        }
          md_number_to_chars (buf, newval, THUMB_SIZE);
        }

+      else
+       {
+         if (value & ~0x7e)
+           as_bad_where (fixP->fx_file, fixP->fx_line,
+                         _("branch out of range"));
+
+          if (fixP->fx_done || !seg->use_rela_p)
+           {
+             newval = md_chars_to_number (buf, THUMB_SIZE);
+             newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
+             md_number_to_chars (buf, newval, THUMB_SIZE);
+           }
+       }

       break;
 
     case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
       break;
 
     case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */


@@ -19291,9 +19594,9 @@ md_begin (void)
 
   if (!mfpu_opt)
     {
 
   if (!mfpu_opt)
     {

-      if (!mcpu_cpu_opt)
+      if (mcpu_cpu_opt != NULL)

        mfpu_opt = &fpu_default;
        mfpu_opt = &fpu_default;

-      else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
+      else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))

        mfpu_opt = &fpu_arch_vfp_v2;
       else
        mfpu_opt = &fpu_arch_fpa;
        mfpu_opt = &fpu_arch_vfp_v2;
       else
        mfpu_opt = &fpu_arch_fpa;


@@ -20300,65 +20603,54 @@ aeabi_set_public_attributes (void)
          for (i = 0; p[i]; i++)
            p[i] = TOUPPER (p[i]);
        }
          for (i = 0; p[i]; i++)
            p[i] = TOUPPER (p[i]);
        }

-      elf32_arm_add_eabi_attr_string (stdoutput, 5, p);
+      bfd_elf_add_proc_attr_string (stdoutput, 5, p);

     }
   /* Tag_CPU_arch.  */
     }
   /* Tag_CPU_arch.  */

-  elf32_arm_add_eabi_attr_int (stdoutput, 6, arch);
+  bfd_elf_add_proc_attr_int (stdoutput, 6, arch);

   /* Tag_CPU_arch_profile.  */
   if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
   /* Tag_CPU_arch_profile.  */
   if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))

-    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'A');
+    bfd_elf_add_proc_attr_int (stdoutput, 7, 'A');

   else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
   else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))

-    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'R');
+    bfd_elf_add_proc_attr_int (stdoutput, 7, 'R');

   else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m))
   else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m))

-    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'M');
+    bfd_elf_add_proc_attr_int (stdoutput, 7, 'M');

   /* Tag_ARM_ISA_use.  */
   if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
   /* Tag_ARM_ISA_use.  */
   if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))

-    elf32_arm_add_eabi_attr_int (stdoutput, 8, 1);
+    bfd_elf_add_proc_attr_int (stdoutput, 8, 1);

   /* Tag_THUMB_ISA_use.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
   /* Tag_THUMB_ISA_use.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))

-    elf32_arm_add_eabi_attr_int (stdoutput, 9,
+    bfd_elf_add_proc_attr_int (stdoutput, 9,

        ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
   /* Tag_VFP_arch.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3)
       || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3))
        ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
   /* Tag_VFP_arch.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3)
       || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3))

-    elf32_arm_add_eabi_attr_int (stdoutput, 10, 3);
+    bfd_elf_add_proc_attr_int (stdoutput, 10, 3);

   else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2)
            || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2))
   else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2)
            || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2))

-    elf32_arm_add_eabi_attr_int (stdoutput, 10, 2);
+    bfd_elf_add_proc_attr_int (stdoutput, 10, 2);

   else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1)
            || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1)
            || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd)
            || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd))
   else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1)
            || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1)
            || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd)
            || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd))

-    elf32_arm_add_eabi_attr_int (stdoutput, 10, 1);
+    bfd_elf_add_proc_attr_int (stdoutput, 10, 1);

   /* Tag_WMMX_arch.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
       || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
   /* Tag_WMMX_arch.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
       || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))

-    elf32_arm_add_eabi_attr_int (stdoutput, 11, 1);
+    bfd_elf_add_proc_attr_int (stdoutput, 11, 1);

   /* Tag_NEON_arch.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1)
       || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1))
   /* Tag_NEON_arch.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1)
       || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1))

-    elf32_arm_add_eabi_attr_int (stdoutput, 12, 1);
+    bfd_elf_add_proc_attr_int (stdoutput, 12, 1);

 }
 
 }
 

-/* Add the .ARM.attributes section.  */
+/* Add the default contents for the .ARM.attributes section.  */

 void
 arm_md_end (void)
 {
 void
 arm_md_end (void)
 {

-  segT s;
-  char *p;
-  addressT addr;
-  offsetT size;
-  

   if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
     return;
 
   aeabi_set_public_attributes ();
   if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
     return;
 
   aeabi_set_public_attributes ();

-  size = elf32_arm_eabi_attr_size (stdoutput);
-  s = subseg_new (".ARM.attributes", 0);
-  bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA);
-  addr = frag_now_fix ();
-  p = frag_more (size);
-  elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size);

 }
 #endif /* OBJ_ELF */
 
 }
 #endif /* OBJ_ELF */
 


@@ -20499,3 +20791,9 @@ s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
   ignore_rest_of_line ();
 }
 
   ignore_rest_of_line ();
 }
 

+/* Copy symbol information.  */
+void
+arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
+{
+  ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
+}