+ long long insn = NOP2;
+ char *f;
+ int i, j, where;
+
+ if (exec_type == EXEC_SEQ
+ && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR))
+ && ((opcode1->op->flags_used & FLAG_DELAY) == 0)
+ && ((opcode1->ecc == ECC_AL) || ! Optimizing))
+ {
+ /* Unconditional, non-delayed branches kill instructions in
+ the right bin. Conditional branches don't always but if
+ we are not optimizing, then we have been asked to produce
+ an error about such constructs. For the purposes of this
+ test, subroutine calls are considered to be branches. */
+ write_1_short (opcode1, insn1, fx->next, FALSE);
+ return 1;
+ }
+
+ /* Note: we do not have to worry about subroutine calls occurring
+ in the right hand container. The return address is always
+ aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
+ switch (exec_type)
+ {
+ case EXEC_UNKNOWN: /* Order not specified. */
+ if (Optimizing
+ && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)
+ && ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU
+ || opcode1->op->unit == MU)
+ &&
+ ( opcode2->op->unit == EITHER_BUT_PREFER_MU
+ || opcode2->op->unit == MU)))
+ {
+ /* Parallel. */
+ exec_type = EXEC_PARALLEL;
+
+ if (opcode1->op->unit == IU
+ || opcode2->op->unit == MU
+ || opcode2->op->unit == EITHER_BUT_PREFER_MU)
+ insn = FM00 | (insn2 << 32) | insn1;
+ else
+ {
+ insn = FM00 | (insn1 << 32) | insn2;
+ fx = fx->next;
+ }
+ }
+ else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)
+ && ((opcode1->op->flags_used & FLAG_DELAY) == 0))
+ || opcode1->op->flags_used & FLAG_RP)
+ {
+ /* We must emit (non-delayed) branch type instructions
+ on their own with nothing in the right container. */
+ /* We must treat repeat instructions likewise, since the
+ following instruction has to be separate from the repeat
+ in order to be repeated. */
+ write_1_short (opcode1, insn1, fx->next, FALSE);
+ return 1;
+ }
+ else if (prev_left_kills_right_p)
+ {
+ /* The left instruction kills the right slot, so we
+ must leave it empty. */
+ write_1_short (opcode1, insn1, fx->next, FALSE);
+ return 1;
+ }
+ else if (opcode1->op->unit == IU)
+ {
+ if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
+ {
+ /* Case 103810 is a request from Mitsubishi that opcodes
+ with EITHER_BUT_PREFER_MU should not be executed in
+ reverse sequential order. */
+ write_1_short (opcode1, insn1, fx->next, FALSE);
+ return 1;
+ }
+
+ /* Reverse sequential. */
+ insn = FM10 | (insn2 << 32) | insn1;
+ exec_type = EXEC_REVSEQ;
+ }
+ else
+ {
+ /* Sequential. */
+ insn = FM01 | (insn1 << 32) | insn2;
+ fx = fx->next;
+ exec_type = EXEC_SEQ;
+ }
+ break;
+
+ case EXEC_PARALLEL: /* Parallel. */
+ flag_explicitly_parallel = flag_xp_state;
+ if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
+ as_bad (_("Instructions may not be executed in parallel"));
+ else if (opcode1->op->unit == IU)
+ {
+ if (opcode2->op->unit == IU)
+ as_bad (_("Two IU instructions may not be executed in parallel"));
+ as_warn (_("Swapping instruction order"));
+ insn = FM00 | (insn2 << 32) | insn1;
+ }
+ else if (opcode2->op->unit == MU)
+ {
+ if (opcode1->op->unit == MU)
+ as_bad (_("Two MU instructions may not be executed in parallel"));
+ else if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
+ as_warn (_("Executing %s in IU may not work"), opcode1->op->name);
+ as_warn (_("Swapping instruction order"));
+ insn = FM00 | (insn2 << 32) | insn1;
+ }
+ else
+ {
+ if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
+ as_warn (_("Executing %s in IU may not work in parallel execution"),
+ opcode2->op->name);
+
+ insn = FM00 | (insn1 << 32) | insn2;
+ fx = fx->next;
+ }
+ flag_explicitly_parallel = 0;
+ break;
+
+ case EXEC_SEQ: /* Sequential. */
+ if (opcode1->op->unit == IU)
+ as_bad (_("IU instruction may not be in the left container"));
+ if (prev_left_kills_right_p)
+ as_bad (_("special left instruction `%s' kills instruction "
+ "`%s' in right container"),
+ opcode1->op->name, opcode2->op->name);
+ insn = FM01 | (insn1 << 32) | insn2;
+ fx = fx->next;
+ break;
+
+ case EXEC_REVSEQ: /* Reverse sequential. */
+ if (opcode2->op->unit == MU)
+ as_bad (_("MU instruction may not be in the right container"));
+ if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
+ as_warn (_("Executing %s in reverse serial with %s may not work"),
+ opcode1->op->name, opcode2->op->name);
+ else if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
+ as_warn (_("Executing %s in IU in reverse serial may not work"),
+ opcode2->op->name);
+ insn = FM10 | (insn1 << 32) | insn2;
+ fx = fx->next;
+ break;
+
+ default:
+ as_fatal (_("unknown execution type passed to write_2_short()"));
+ }
+
+ f = frag_more (8);
+ dwarf2_emit_insn (8);
+ d30v_number_to_chars (f, insn, 8);
+
+ /* If the previous instruction was a 32-bit multiply but it is put into a
+ parallel container, mark the current instruction as being a 32-bit
+ multiply. */
+ if (prev_mul32_p && exec_type == EXEC_PARALLEL)
+ cur_mul32_p = 1;
+
+ for (j = 0; j < 2; j++)
+ {
+ for (i = 0; i < fx->fc; i++)
+ {
+ if (fx->fix[i].reloc)
+ {
+ where = (f - frag_now->fr_literal) + 4 * j;
+
+ fix_new_exp (frag_now,
+ where,
+ fx->fix[i].size,
+ &(fx->fix[i].exp),
+ fx->fix[i].pcrel,
+ fx->fix[i].reloc);
+ }
+ }
+
+ fx->fc = 0;
+ fx = fx->next;
+ }
+
+ return 0;
+}
+
+/* Get a pointer to an entry in the format table.
+ It must look at all formats for an opcode and use the operands
+ to choose the correct one. Return NULL on error. */
+
+static struct d30v_format *
+find_format (struct d30v_opcode *opcode,
+ expressionS myops[],
+ int fsize,
+ int cmp_hack)
+{
+ int match, opcode_index, i = 0, j, k;
+ struct d30v_format *fm;
+
+ if (opcode == NULL)
+ return NULL;
+
+ /* Get all the operands and save them as expressions. */
+ get_operands (myops, cmp_hack);
+
+ while ((opcode_index = opcode->format[i++]) != 0)
+ {
+ if (fsize == FORCE_SHORT && opcode_index >= LONG)
+ continue;
+
+ if (fsize == FORCE_LONG && opcode_index < LONG)
+ continue;
+
+ fm = (struct d30v_format *) &d30v_format_table[opcode_index];
+ k = opcode_index;
+ while (fm->form == opcode_index)
+ {
+ match = 1;
+ /* Now check the operands for compatibility. */
+ for (j = 0; match && fm->operands[j]; j++)
+ {
+ int flags = d30v_operand_table[fm->operands[j]].flags;
+ int bits = d30v_operand_table[fm->operands[j]].bits;
+ operatorT X_op = myops[j].X_op;
+ int num = myops[j].X_add_number;
+
+ if (flags & OPERAND_SPECIAL)
+ break;
+ else if (X_op == O_illegal)
+ match = 0;
+ else if (flags & OPERAND_REG)
+ {
+ if (X_op != O_register
+ || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC))
+ || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC))
+ || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG))
+ || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG))
+ || ((flags & OPERAND_CONTROL)
+ && !(num & (OPERAND_CONTROL | OPERAND_FLAG))))
+ match = 0;
+ }
+ else if (((flags & OPERAND_MINUS)
+ && (X_op != O_absent || num != OPERAND_MINUS))
+ || ((flags & OPERAND_PLUS)
+ && (X_op != O_absent || num != OPERAND_PLUS))
+ || ((flags & OPERAND_ATMINUS)
+ && (X_op != O_absent || num != OPERAND_ATMINUS))
+ || ((flags & OPERAND_ATPAR)
+ && (X_op != O_absent || num != OPERAND_ATPAR))
+ || ((flags & OPERAND_ATSIGN)
+ && (X_op != O_absent || num != OPERAND_ATSIGN)))
+ match = 0;
+ else if (flags & OPERAND_NUM)
+ {
+ /* A number can be a constant or symbol expression. */
+
+ /* If we have found a register name, but that name
+ also matches a symbol, then re-parse the name as
+ an expression. */
+ if (X_op == O_register
+ && symbol_find ((char *) myops[j].X_op_symbol))
+ {
+ input_line_pointer = (char *) myops[j].X_op_symbol;
+ expression (&myops[j]);
+ }
+
+ /* Turn an expression into a symbol for later resolution. */
+ if (X_op != O_absent && X_op != O_constant
+ && X_op != O_symbol && X_op != O_register
+ && X_op != O_big)
+ {
+ symbolS *sym = make_expr_symbol (&myops[j]);
+ myops[j].X_op = X_op = O_symbol;
+ myops[j].X_add_symbol = sym;
+ myops[j].X_add_number = num = 0;
+ }
+
+ if (fm->form >= LONG)
+ {
+ /* If we're testing for a LONG format, either fits. */
+ if (X_op != O_constant && X_op != O_symbol)
+ match = 0;
+ }
+ else if (fm->form < LONG
+ && ((fsize == FORCE_SHORT && X_op == O_symbol)
+ || (fm->form == SHORT_D2 && j == 0)))
+ match = 1;
+
+ /* This is the tricky part. Will the constant or symbol
+ fit into the space in the current format? */
+ else if (X_op == O_constant)
+ {
+ if (check_range (num, bits, flags))
+ match = 0;
+ }
+ else if (X_op == O_symbol
+ && S_IS_DEFINED (myops[j].X_add_symbol)
+ && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg
+ && opcode->reloc_flag == RELOC_PCREL)
+ {
+ /* If the symbol is defined, see if the value will fit
+ into the form we're considering. */
+ fragS *f;
+ long value;
+
+ /* Calculate the current address by running through the
+ previous frags and adding our current offset. */
+ value = frag_now_fix_octets ();
+ for (f = frchain_now->frch_root; f; f = f->fr_next)
+ value += f->fr_fix + f->fr_offset;
+ value = S_GET_VALUE (myops[j].X_add_symbol) - value;
+ if (check_range (value, bits, flags))
+ match = 0;
+ }
+ else
+ match = 0;
+ }
+ }
+ /* We're only done if the operands matched so far AND there
+ are no more to check. */
+ if (match && myops[j].X_op == 0)
+ {
+ /* Final check - issue a warning if an odd numbered register
+ is used as the first register in an instruction that reads
+ or writes 2 registers. */
+
+ for (j = 0; fm->operands[j]; j++)
+ if (myops[j].X_op == O_register
+ && (myops[j].X_add_number & 1)
+ && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG))
+ as_warn (_("Odd numbered register used as target of multi-register instruction"));
+
+ return fm;
+ }
+ fm = (struct d30v_format *) &d30v_format_table[++k];
+ }
+ }
+ return NULL;
+}
+
+/* Assemble a single instruction and return an opcode.
+ Return -1 (an invalid opcode) on error. */
+
+#define NAME_BUF_LEN 20
+
+static long long
+do_assemble (char *str,
+ struct d30v_insn *opcode,
+ int shortp,
+ int is_parallel)
+{
+ char *op_start;
+ char *save;
+ char *op_end;
+ char name[NAME_BUF_LEN];
+ int cmp_hack;
+ int nlen = 0;
+ int fsize = (shortp ? FORCE_SHORT : 0);
+ expressionS myops[6];
+ long long insn;
+
+ /* Drop leading whitespace. */
+ while (*str == ' ')
+ str++;
+
+ /* Find the opcode end. */
+ for (op_start = op_end = str;
+ *op_end
+ && nlen < (NAME_BUF_LEN - 1)
+ && *op_end != '/'
+ && !is_end_of_line[(unsigned char) *op_end] && *op_end != ' ';
+ op_end++)
+ {
+ name[nlen] = TOLOWER (op_start[nlen]);
+ nlen++;
+ }
+
+ if (nlen == 0)
+ return -1;
+
+ name[nlen] = 0;
+
+ /* If there is an execution condition code, handle it. */
+ if (*op_end == '/')
+ {
+ int i = 0;
+ while ((i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2))
+ i++;
+
+ if (i == ECC_MAX)
+ {
+ char tmp[4];
+ strncpy (tmp, op_end + 1, 2);
+ tmp[2] = 0;
+ as_bad (_("unknown condition code: %s"), tmp);
+ return -1;
+ }
+ opcode->ecc = i;
+ op_end += 3;
+ }
+ else
+ opcode->ecc = ECC_AL;
+
+ /* CMP and CMPU change their name based on condition codes. */
+ if (!strncmp (name, "cmp", 3))
+ {
+ int p, i;
+ char **d30v_str = (char **) d30v_cc_names;
+
+ if (name[3] == 'u')
+ p = 4;
+ else
+ p = 3;
+
+ for (i = 1; *d30v_str && strncmp (*d30v_str, &name[p], 2); i++, d30v_str++)
+ ;
+
+ /* cmpu only supports some condition codes. */
+ if (p == 4)
+ {
+ if (i < 3 || i > 6)
+ {
+ name[p + 2] = 0;
+ as_bad (_("cmpu doesn't support condition code %s"), &name[p]);
+ }
+ }
+
+ if (!*d30v_str)
+ {
+ name[p + 2] = 0;
+ as_bad (_("unknown condition code: %s"), &name[p]);
+ }
+
+ cmp_hack = i;
+ name[p] = 0;
+ }
+ else
+ cmp_hack = 0;
+
+ /* Need to look for .s or .l. */
+ if (name[nlen - 2] == '.')
+ {
+ switch (name[nlen - 1])
+ {
+ case 's':
+ fsize = FORCE_SHORT;
+ break;
+ case 'l':
+ fsize = FORCE_LONG;
+ break;
+ }
+ name[nlen - 2] = 0;
+ }
+
+ /* Find the first opcode with the proper name. */
+ opcode->op = (struct d30v_opcode *) hash_find (d30v_hash, name);
+ if (opcode->op == NULL)
+ {
+ as_bad (_("unknown opcode: %s"), name);
+ return -1;
+ }
+
+ save = input_line_pointer;
+ input_line_pointer = op_end;
+ while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack)))
+ {
+ opcode->op++;
+ if (opcode->op->name == NULL || strcmp (opcode->op->name, name))
+ {
+ as_bad (_("operands for opcode `%s' do not match any valid format"),
+ name);
+ return -1;
+ }
+ }
+ input_line_pointer = save;
+
+ insn = build_insn (opcode, myops);
+
+ /* Propagate multiply status. */
+ if (insn != -1)
+ {
+ if (is_parallel && prev_mul32_p)
+ cur_mul32_p = 1;
+ else
+ {
+ prev_mul32_p = cur_mul32_p;
+ cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0;
+ }
+ }
+
+ /* Propagate left_kills_right status. */
+ if (insn != -1)
+ {
+ prev_left_kills_right_p = cur_left_kills_right_p;
+
+ if (opcode->op->flags_set & FLAG_LKR)
+ {
+ cur_left_kills_right_p = 1;
+
+ if (strcmp (opcode->op->name, "mvtsys") == 0)
+ {
+ /* Left kills right for only mvtsys only for
+ PSW/PSWH/PSWL/flags target. */
+ if ((myops[0].X_op == O_register) &&
+ ((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */
+ (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */
+ (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */
+ (myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */
+ (myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */
+ (myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */
+ (myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */
+ (myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */
+ (myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */
+ (myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */
+ (myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */
+ {
+ cur_left_kills_right_p = 1;
+ }
+ else
+ {
+ /* Other mvtsys target registers don't kill right
+ instruction. */
+ cur_left_kills_right_p = 0;
+ }
+ } /* mvtsys */
+ }
+ else
+ cur_left_kills_right_p = 0;
+ }
+
+ return insn;
+}
+
+/* Called internally to handle all alignment needs. This takes care
+ of eliding calls to frag_align if'n the cached current alignment
+ says we've already got it, as well as taking care of the auto-aligning
+ labels wrt code. */
+
+static void
+d30v_align (int n, char *pfill, symbolS *label)
+{
+ /* The front end is prone to changing segments out from under us
+ temporarily when -g is in effect. */
+ int switched_seg_p = (d30v_current_align_seg != now_seg);
+
+ /* Do not assume that if 'd30v_current_align >= n' and
+ '! switched_seg_p' that it is safe to avoid performing
+ this alignment request. The alignment of the current frag
+ can be changed under our feet, for example by a .ascii
+ directive in the source code. cf testsuite/gas/d30v/reloc.s */
+ d30v_cleanup (FALSE);
+
+ if (pfill == NULL)
+ {
+ if (n > 2
+ && (bfd_section_flags (now_seg) & SEC_CODE) != 0)
+ {
+ static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 };
+
+ /* First, make sure we're on a four-byte boundary, in case
+ someone has been putting .byte values the text section. */
+ if (d30v_current_align < 2 || switched_seg_p)
+ frag_align (2, 0, 0);
+ frag_align_pattern (n, nop, sizeof nop, 0);
+ }
+ else
+ frag_align (n, 0, 0);
+ }
+ else
+ frag_align (n, *pfill, 0);
+
+ if (!switched_seg_p)
+ d30v_current_align = n;
+
+ if (label != NULL)
+ {
+ symbolS *sym;
+ int label_seen = FALSE;
+ struct frag *old_frag;
+ valueT old_value;
+ valueT new_value;
+
+ gas_assert (S_GET_SEGMENT (label) == now_seg);
+
+ old_frag = symbol_get_frag (label);
+ old_value = S_GET_VALUE (label);
+ new_value = (valueT) frag_now_fix ();
+
+ /* It is possible to have more than one label at a particular
+ address, especially if debugging is enabled, so we must
+ take care to adjust all the labels at this address in this
+ fragment. To save time we search from the end of the symbol
+ list, backwards, since the symbols we are interested in are
+ almost certainly the ones that were most recently added.
+ Also to save time we stop searching once we have seen at least
+ one matching label, and we encounter a label that is no longer
+ in the target fragment. Note, this search is guaranteed to
+ find at least one match when sym == label, so no special case
+ code is necessary. */
+ for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym))
+ {
+ if (symbol_get_frag (sym) == old_frag
+ && S_GET_VALUE (sym) == old_value)
+ {
+ label_seen = TRUE;
+ symbol_set_frag (sym, frag_now);
+ S_SET_VALUE (sym, new_value);
+ }
+ else if (label_seen && symbol_get_frag (sym) != old_frag)
+ break;
+ }
+ }
+
+ record_alignment (now_seg, n);
+}
+
+/* This is the main entry point for the machine-dependent assembler.
+ STR points to a machine-dependent instruction. This function is
+ supposed to emit the frags/bytes it assembles to. For the D30V, it
+ mostly handles the special VLIW parsing and packing and leaves the
+ difficult stuff to do_assemble (). */
+
+static long long prev_insn = -1;
+static struct d30v_insn prev_opcode;
+static subsegT prev_subseg;
+static segT prev_seg = 0;
+
+void
+md_assemble (char *str)
+{
+ struct d30v_insn opcode;
+ long long insn;
+ /* Execution type; parallel, etc. */
+ exec_type_enum extype = EXEC_UNKNOWN;