+ int i, j, shift, regno, bits, ecc;
+ unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2;
+ unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2];
+ struct d30v_format *f;
+ struct d30v_opcode *op;
+
+ /* Section 4.3: Both instructions must not be IU or MU only. */
+ if ((op1->op->unit == IU && op2->op->unit == IU)
+ || (op1->op->unit == MU && op2->op->unit == MU))
+ return 0;
+
+ /* First instruction must not be a jump to safely optimize, unless this
+ is an explicit parallel operation. */
+ if (exec_type != EXEC_PARALLEL
+ && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR)))
+ return 0;
+
+ /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
+ then it is safe to allow the two to be done as parallel ops, since only
+ one will ever be executed at a time. */
+ if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX)
+ || (op1->ecc == ECC_FX && op2->ecc == ECC_TX)
+ || (op1->ecc == ECC_XT && op2->ecc == ECC_XF)
+ || (op1->ecc == ECC_XF && op2->ecc == ECC_XT))
+ return 1;
+
+ /* [0] r0-r31
+ [1] r32-r63
+ [2] a0, a1, flag registers. */
+ for (j = 0; j < 2; j++)
+ {
+ if (j == 0)
+ {
+ f = op1->form;
+ op = op1->op;
+ ecc = op1->ecc;
+ ins = insn1;
+ }
+ else
+ {
+ f = op2->form;
+ op = op2->op;
+ ecc = op2->ecc;
+ ins = insn2;
+ }
+
+ flag_reg[j] = 0;
+ mod_reg[j][0] = mod_reg[j][1] = 0;
+ used_reg[j][0] = used_reg[j][1] = 0;
+
+ if (flag_explicitly_parallel)
+ {
+ /* For human specified parallel instructions we have been asked
+ to ignore the possibility that both instructions could modify
+ bits in the PSW, so we initialise the mod & used arrays to 0.
+ We have been asked, however, to refuse to allow parallel
+ instructions which explicitly set the same flag register,
+ eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
+ for the use of a flag register and set a bit in the mod or used
+ array appropriately. */
+ mod_reg[j][2] = 0;
+ used_reg[j][2] = 0;
+ }
+ else
+ {
+ mod_reg[j][2] = (op->flags_set & FLAG_ALL);
+ used_reg[j][2] = (op->flags_used & FLAG_ALL);
+ }
+
+ /* BSR/JSR always sets R62. */
+ if (op->flags_used & FLAG_JSR)
+ mod_reg[j][1] = (1L << (62 - 32));
+
+ /* Conditional execution affects the flags_used. */
+ switch (ecc)
+ {
+ case ECC_TX:
+ case ECC_FX:
+ used_reg[j][2] |= flag_reg[j] = FLAG_0;
+ break;
+
+ case ECC_XT:
+ case ECC_XF:
+ used_reg[j][2] |= flag_reg[j] = FLAG_1;
+ break;
+
+ case ECC_TT:
+ case ECC_TF:
+ used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1);
+ break;
+ }
+
+ for (i = 0; f->operands[i]; i++)
+ {
+ flags = d30v_operand_table[f->operands[i]].flags;
+ shift = 12 - d30v_operand_table[f->operands[i]].position;
+ bits = d30v_operand_table[f->operands[i]].bits;
+ if (bits == 32)
+ mask = 0xffffffff;
+ else
+ mask = 0x7FFFFFFF >> (31 - bits);
+
+ if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS))
+ {
+ /* This is a post-increment or post-decrement.
+ The previous register needs to be marked as modified. */
+ shift = 12 - d30v_operand_table[f->operands[i - 1]].position;
+ regno = (ins >> shift) & 0x3f;
+ if (regno >= 32)
+ mod_reg[j][1] |= 1L << (regno - 32);
+ else
+ mod_reg[j][0] |= 1L << regno;
+ }
+ else if (flags & OPERAND_REG)
+ {
+ regno = (ins >> shift) & mask;
+ /* The memory write functions don't have a destination
+ register. */
+ if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM))
+ {
+ /* MODIFIED registers and flags. */
+ if (flags & OPERAND_ACC)
+ {
+ if (regno == 0)
+ mod_reg[j][2] |= FLAG_A0;
+ else if (regno == 1)
+ mod_reg[j][2] |= FLAG_A1;
+ else
+ abort ();
+ }
+ else if (flags & OPERAND_FLAG)
+ mod_reg[j][2] |= 1L << regno;
+ else if (!(flags & OPERAND_CONTROL))
+ {
+ int r, z;
+
+ /* Need to check if there are two destination
+ registers, for example ld2w. */
+ if (flags & OPERAND_2REG)
+ z = 1;
+ else
+ z = 0;
+
+ for (r = regno; r <= regno + z; r++)
+ {
+ if (r >= 32)
+ mod_reg[j][1] |= 1L << (r - 32);
+ else
+ mod_reg[j][0] |= 1L << r;
+ }
+ }
+ }
+ else
+ {
+ /* USED, but not modified registers and flags. */
+ if (flags & OPERAND_ACC)
+ {
+ if (regno == 0)
+ used_reg[j][2] |= FLAG_A0;
+ else if (regno == 1)
+ used_reg[j][2] |= FLAG_A1;
+ else
+ abort ();
+ }
+ else if (flags & OPERAND_FLAG)
+ used_reg[j][2] |= 1L << regno;
+ else if (!(flags & OPERAND_CONTROL))
+ {
+ int r, z;
+
+ /* Need to check if there are two source
+ registers, for example st2w. */
+ if (flags & OPERAND_2REG)
+ z = 1;
+ else
+ z = 0;
+
+ for (r = regno; r <= regno + z; r++)
+ {
+ if (r >= 32)
+ used_reg[j][1] |= 1L << (r - 32);
+ else
+ used_reg[j][0] |= 1L << r;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ flags_set1 = op1->op->flags_set;
+ flags_set2 = op2->op->flags_set;
+ flags_used1 = op1->op->flags_used;
+ flags_used2 = op2->op->flags_used;
+
+ /* Check for illegal combinations with ADDppp/SUBppp. */
+ if (((flags_set1 & FLAG_NOT_WITH_ADDSUBppp) != 0
+ && (flags_used2 & FLAG_ADDSUBppp) != 0)
+ || ((flags_set2 & FLAG_NOT_WITH_ADDSUBppp) != 0
+ && (flags_used1 & FLAG_ADDSUBppp) != 0))
+ return 0;