+static int
+i386_intel_simplify_register (expressionS *e)
+{
+ int reg_num;
+
+ if (this_operand < 0 || intel_state.in_offset)
+ {
+ as_bad (_("invalid use of register"));
+ return 0;
+ }
+
+ if (e->X_op == O_register)
+ reg_num = e->X_add_number;
+ else
+ reg_num = e->X_md - 1;
+
+ if (reg_num < 0 || reg_num >= (int) i386_regtab_size)
+ {
+ as_bad (_("invalid register number"));
+ return 0;
+ }
+
+ if (!intel_state.in_bracket)
+ {
+ if (i.op[this_operand].regs)
+ {
+ as_bad (_("invalid use of register"));
+ return 0;
+ }
+ if (i386_regtab[reg_num].reg_type.bitfield.sreg3
+ && i386_regtab[reg_num].reg_num == RegFlat)
+ {
+ as_bad (_("invalid use of pseudo-register"));
+ return 0;
+ }
+ i.op[this_operand].regs = i386_regtab + reg_num;
+ }
+ else if (!intel_state.index
+ && (i386_regtab[reg_num].reg_type.bitfield.xmmword
+ || i386_regtab[reg_num].reg_type.bitfield.ymmword
+ || i386_regtab[reg_num].reg_type.bitfield.zmmword
+ || i386_regtab[reg_num].reg_num == RegIZ))
+ intel_state.index = i386_regtab + reg_num;
+ else if (!intel_state.base && !intel_state.in_scale)
+ intel_state.base = i386_regtab + reg_num;
+ else if (!intel_state.index)
+ {
+ if (intel_state.in_scale
+ || current_templates->start->base_opcode == 0xf30f1b /* bndmk */
+ || (current_templates->start->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */
+ || i386_regtab[reg_num].reg_type.bitfield.baseindex)
+ intel_state.index = i386_regtab + reg_num;
+ else
+ {
+ /* Convert base to index and make ESP/RSP the base. */
+ intel_state.index = intel_state.base;
+ intel_state.base = i386_regtab + reg_num;
+ }
+ }
+ else
+ {
+ /* esp is invalid as index */
+ intel_state.index = i386_regtab + REGNAM_EAX + ESP_REG_NUM;
+ }
+ return 2;
+}
+