+/* Check if operands are valid for the instruction. */
+
+static int
+check_VecOperands (const insn_template *t)
+{
+ /* Without VSIB byte, we can't have a vector register for index. */
+ if (!t->opcode_modifier.vecsib
+ && i.index_reg
+ && (i.index_reg->reg_type.bitfield.regxmm
+ || i.index_reg->reg_type.bitfield.regymm))
+ {
+ i.error = unsupported_vector_index_register;
+ return 1;
+ }
+
+ /* For VSIB byte, we need a vector register for index and no PC
+ relative addressing is allowed. */
+ if (t->opcode_modifier.vecsib
+ && (!i.index_reg
+ || !((t->opcode_modifier.vecsib == VecSIB128
+ && i.index_reg->reg_type.bitfield.regxmm)
+ || (t->opcode_modifier.vecsib == VecSIB256
+ && i.index_reg->reg_type.bitfield.regymm))
+ || (i.base_reg && i.base_reg->reg_num == RegRip)))
+ {
+ i.error = invalid_vsib_address;
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Check if operands are valid for the instruction. Update VEX