- source = 1;
- reg = 0;
-
- /* This instruction must have 4 operands: 4 register operands
- or 3 register operands plus 1 memory operand. It must have
- VexNDS and VexImmExt. */
- assert (i.operands == 4
- && (i.reg_operands == 4
- || (i.reg_operands == 3 && i.mem_operands == 1))
- && i.tm.opcode_modifier.vexnds
- && i.tm.opcode_modifier.veximmext
- && (operand_type_equal (&i.tm.operand_types[dest],
- ®xmm)
- || operand_type_equal (&i.tm.operand_types[dest],
- ®ymm))
- && (operand_type_equal (&i.tm.operand_types[nds],
- ®xmm)
- || operand_type_equal (&i.tm.operand_types[nds],
- ®ymm))
- && (operand_type_equal (&i.tm.operand_types[reg],
- ®xmm)
- || operand_type_equal (&i.tm.operand_types[reg],
- ®ymm)));
+
+ /* This instruction must have 4 register operands
+ or 3 register operands plus 1 memory operand.
+ It must have VexNDS and VexImmExt. */
+ gas_assert ((i.reg_operands == 4
+ || (i.reg_operands == 3 && i.mem_operands == 1))
+ && i.tm.opcode_modifier.vexnds
+ && i.tm.opcode_modifier.veximmext
+ && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
+ || operand_type_equal (&i.tm.operand_types[dest], ®ymm)));