- /* Register name in an expression */
- /* FIXME: this isn't much of a check any more. */
- expP->X_op = O_illegal;
- }
-
- input_line_pointer = save_in; /* Restore global */
- }
-}
-
-
-/*****************************************************************************
- parse_ldcont:
- Parse and replace a 'ldconst' pseudo-instruction with an appropriate
- i80960 instruction.
-
- Assumes the input consists of:
- arg[0] opcode mnemonic ('ldconst')
- arg[1] first operand (constant)
- arg[2] name of register to be loaded
-
- Replaces opcode and/or operands as appropriate.
-
- Returns the new number of arguments, or -1 on failure.
-
- *************************************************************************** */
-static
-int
-parse_ldconst (arg)
- char *arg[]; /* See above */
-{
- int n; /* Constant to be loaded */
- int shift; /* Shift count for "shlo" instruction */
- static char buf[5]; /* Literal for first operand */
- static char buf2[5]; /* Literal for second operand */
- expressionS e; /* Parsed expression */
-
-
- arg[3] = NULL; /* So we can tell at the end if it got used or not */
-
- parse_expr (arg[1], &e);
- switch (e.X_op)
- {
- default:
- /* We're dependent on one or more symbols -- use "lda" */
- arg[0] = "lda";
- break;
-
- case O_constant:
- /* Try the following mappings:
- * ldconst 0,<reg> ->mov 0,<reg>
- * ldconst 31,<reg> ->mov 31,<reg>
- * ldconst 32,<reg> ->addo 1,31,<reg>
- * ldconst 62,<reg> ->addo 31,31,<reg>
- * ldconst 64,<reg> ->shlo 8,3,<reg>
- * ldconst -1,<reg> ->subo 1,0,<reg>
- * ldconst -31,<reg>->subo 31,0,<reg>
- *
- * anthing else becomes:
- * lda xxx,<reg>
- */
- n = offs (e);
- if ((0 <= n) && (n <= 31))
- {
- arg[0] = "mov";
-
- }
- else if ((-31 <= n) && (n <= -1))
- {
- arg[0] = "subo";
- arg[3] = arg[2];
- sprintf (buf, "%d", -n);
- arg[1] = buf;
- arg[2] = "0";
-
- }
- else if ((32 <= n) && (n <= 62))
- {
- arg[0] = "addo";
- arg[3] = arg[2];
- arg[1] = "31";
- sprintf (buf, "%d", n - 31);
- arg[2] = buf;
-
- }
- else if ((shift = shift_ok (n)) != 0)
- {
- arg[0] = "shlo";
- arg[3] = arg[2];
- sprintf (buf, "%d", shift);
- arg[1] = buf;
- sprintf (buf2, "%d", n >> shift);
- arg[2] = buf2;
-
- }
- else
- {
- arg[0] = "lda";
- }
- break;
-
- case O_illegal:
- as_bad (_("invalid constant"));
- return -1;
- break;
- }
- return (arg[3] == 0) ? 2 : 3;
-}
-
-/*****************************************************************************
- parse_memop: parse a memory operand
-
- This routine is based on the observation that the 4 mode bits of the
- MEMB format, taken individually, have fairly consistent meaning:
-
- M3 (bit 13): 1 if displacement is present (D_BIT)
- M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
- M1 (bit 11): 1 if index is present (I_BIT)
- M0 (bit 10): 1 if abase is present (A_BIT)
-
- So we parse the memory operand and set bits in the mode as we find
- things. Then at the end, if we go to MEMB format, we need only set
- the MEMB bit (M2) and our mode is built for us.
-
- Unfortunately, I said "fairly consistent". The exceptions:
-
- DBIA
- 0100 Would seem illegal, but means "abase-only".
-
- 0101 Would seem to mean "abase-only" -- it means IP-relative.
- Must be converted to 0100.
-
- 0110 Would seem to mean "index-only", but is reserved.
- We turn on the D bit and provide a 0 displacement.
-
- The other thing to observe is that we parse from the right, peeling
- things * off as we go: first any index spec, then any abase, then
- the displacement.
-
- *************************************************************************** */
-static
-void
-parse_memop (memP, argP, optype)
- memS *memP; /* Where to put the results */
- char *argP; /* Text of the operand to be parsed */
- int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
-{
- char *indexP; /* Pointer to index specification with "[]" removed */
- char *p; /* Temp char pointer */
- char iprel_flag; /* True if this is an IP-relative operand */
- int regnum; /* Register number */
- /* Scale factor: 1,2,4,8, or 16. Later converted to internal format
- (0,1,2,3,4 respectively). */
- int scale;
- int mode; /* MEMB mode bits */
- int *intP; /* Pointer to register number */
-
- /* The following table contains the default scale factors for each
- type of memory instruction. It is accessed using (optype-MEM1)
- as an index -- thus it assumes the 'optype' constants are
- assigned consecutive values, in the order they appear in this
- table. */
- static const int def_scale[] =
- {
- 1, /* MEM1 */
- 2, /* MEM2 */
- 4, /* MEM4 */
- 8, /* MEM8 */
- -1, /* MEM12 -- no valid default */
- 16 /* MEM16 */
- };
-
-
- iprel_flag = mode = 0;
-
- /* Any index present? */
- indexP = get_ispec (argP);
- if (indexP)
- {
- p = strchr (indexP, '*');
- if (p == NULL)
- {
- /* No explicit scale -- use default for this instruction
- type and assembler mode. */
- if (flag_mri)
- scale = 1;
- else
- /* GNU960 compatibility */
- scale = def_scale[optype - MEM1];
- }
- else
- {
- *p++ = '\0'; /* Eliminate '*' */
-
- /* Now indexP->a '\0'-terminated register name,
- * and p->a scale factor.
- */
-
- if (!strcmp (p, "16"))
- {
- scale = 16;
- }
- else if (strchr ("1248", *p) && (p[1] == '\0'))
- {
- scale = *p - '0';
- }
- else
- {
- scale = -1;
- }
- }
-
- regnum = get_regnum (indexP); /* Get index reg. # */
- if (!IS_RG_REG (regnum))
- {
- as_bad (_("invalid index register"));
- return;
- }
-
- /* Convert scale to its binary encoding */
- switch (scale)
- {
- case 1:
- scale = 0 << 7;