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gdb: Convert language la_word_break_characters field to a method
[deliverable/binutils-gdb.git]
/
gas
/
config
/
tc-mep.c
diff --git
a/gas/config/tc-mep.c
b/gas/config/tc-mep.c
index 3a6bd6a7d465014412f4bc69ebca83305e2e2132..6b52841fa9dacd799cb174a9fe021258007a95af 100644
(file)
--- a/
gas/config/tc-mep.c
+++ b/
gas/config/tc-mep.c
@@
-1,6
+1,5
@@
/* tc-mep.c -- Assembler for the Toshiba Media Processor.
/* tc-mep.c -- Assembler for the Toshiba Media Processor.
- Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007, 2009
- Free Software Foundation. Inc.
+ Copyright (C) 2001-2020 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
This file is part of GAS, the GNU Assembler.
@@
-19,8
+18,8
@@
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
-#include <stdio.h>
#include "as.h"
#include "as.h"
+#include <stdio.h>
#include "dwarf2dbg.h"
#include "subsegs.h"
#include "symcat.h"
#include "dwarf2dbg.h"
#include "subsegs.h"
#include "symcat.h"
@@
-29,7
+28,6
@@
#include "cgen.h"
#include "elf/common.h"
#include "elf/mep.h"
#include "cgen.h"
#include "elf/common.h"
#include "elf/mep.h"
-#include "libbfd.h"
#include "xregex.h"
/* Structure to hold all of the different components describing
#include "xregex.h"
/* Structure to hold all of the different components describing
@@
-196,7
+194,7
@@
static int optbits = 0;
static int optbitset = 0;
int
static int optbitset = 0;
int
-md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+md_parse_option (int c, c
onst c
har *arg ATTRIBUTE_UNUSED)
{
int i, idx;
switch (c)
{
int i, idx;
switch (c)
@@
-444,7
+442,7
@@
mep_machine (void)
/* The MeP version of the cgen parse_operand function. The only difference
from the standard version is that we want to avoid treating '$foo' and
'($foo...)' as references to a symbol called '$foo'. The chances are
/* The MeP version of the cgen parse_operand function. The only difference
from the standard version is that we want to avoid treating '$foo' and
'($foo...)' as references to a symbol called '$foo'. The chances are
- that '$foo' is really a misspel
t
register. */
+ that '$foo' is really a misspel
led
register. */
static const char *
mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
static const char *
mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
@@
-466,7
+464,7
@@
mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
}
void
}
void
-md_begin ()
+md_begin (
void
)
{
/* Initialize the `cgen' interface. */
{
/* Initialize the `cgen' interface. */
@@
-487,12
+485,12
@@
md_begin ()
mep_cop = mep_config_map[mep_config_index].cpu_flag & EF_MEP_COP_MASK;
/* Set the machine number and endian. */
mep_cop = mep_config_map[mep_config_index].cpu_flag & EF_MEP_COP_MASK;
/* Set the machine number and endian. */
- gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
+ gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0
U
,
CGEN_CPU_OPEN_ENDIAN,
target_big_endian
? CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE,
CGEN_CPU_OPEN_ENDIAN,
target_big_endian
? CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE,
- CGEN_CPU_OPEN_ISAS, 0,
+ CGEN_CPU_OPEN_ISAS,
(CGEN_BITSET *)
0,
CGEN_CPU_OPEN_END);
mep_cgen_init_asm (gas_cgen_cpu_desc);
CGEN_CPU_OPEN_END);
mep_cgen_init_asm (gas_cgen_cpu_desc);
@@
-509,7
+507,7
@@
md_begin ()
gas_cgen_initialize_saved_fixups_array();
}
gas_cgen_initialize_saved_fixups_array();
}
-/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a
+/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a
coprocessor instruction, if possible, into FIELDS, BUF, and INSN. */
static const CGEN_INSN *
coprocessor instruction, if possible, into FIELDS, BUF, and INSN. */
static const CGEN_INSN *
@@
-524,14
+522,14
@@
mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd,
const char *errmsg = NULL;
/* The instructions are stored in hashed lists. */
const char *errmsg = NULL;
/* The instructions are stored in hashed lists. */
- ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc,
+ ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc,
CGEN_INSN_MNEMONIC (pinsn));
start = str;
for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
{
const CGEN_INSN *insn = ilist->insn;
CGEN_INSN_MNEMONIC (pinsn));
start = str;
for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
{
const CGEN_INSN *insn = ilist->insn;
- if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn),
+ if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn),
CGEN_INSN_MNEMONIC (pinsn)) == 0
&& MEP_INSN_COP_P (ilist->insn)
&& mep_cgen_insn_supported (cd, insn))
CGEN_INSN_MNEMONIC (pinsn)) == 0
&& MEP_INSN_COP_P (ilist->insn)
&& mep_cgen_insn_supported (cd, insn))
@@
-549,7
+547,7
@@
mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd,
errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
if (errmsg != NULL)
continue;
errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
if (errmsg != NULL)
continue;
-
+
errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
(bfd_vma) 0);
if (errmsg != NULL)
errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
(bfd_vma) 0);
if (errmsg != NULL)
@@
-584,7
+582,7
@@
mep_check_parallel32_scheduling (void)
an internally parallel core or an internally parallel coprocessor,
neither of which are supported at this time. */
if ( num_insns_saved > 2 )
an internally parallel core or an internally parallel coprocessor,
neither of which are supported at this time. */
if ( num_insns_saved > 2 )
- as_fatal("Internally paralled cores and coprocessors not supported.");
+ as_fatal("Internally paralle
le
d cores and coprocessors not supported.");
/* If there are no insns saved, that's ok. Just return. This will
happen when mep_process_saved_insns is called when the end of the
/* If there are no insns saved, that's ok. Just return. This will
happen when mep_process_saved_insns is called when the end of the
@@
-613,7
+611,7
@@
mep_check_parallel32_scheduling (void)
as_bad (_("core and copro insn lengths must total 32 bits."));
}
else
as_bad (_("core and copro insn lengths must total 32 bits."));
}
else
- as_bad (_("vliw group must consist of 1 core and 1 copro insn."));
+ as_bad (_("vliw group must consist of 1 core and 1 copro insn."));
}
else
{
}
else
{
@@
-623,7
+621,7
@@
mep_check_parallel32_scheduling (void)
1. The instruction is a 32 bit core or coprocessor insn and
can be executed by itself. Valid.
1. The instruction is a 32 bit core or coprocessor insn and
can be executed by itself. Valid.
- 2. The instrucion is a core instruction for which a cop nop
+ 2. The instruc
t
ion is a core instruction for which a cop nop
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
@@
-649,17
+647,17
@@
mep_check_parallel32_scheduling (void)
CGEN_INSN_VLIW32_NO_MATCHING_NOP))
as_fatal ("No valid nop.");
CGEN_INSN_VLIW32_NO_MATCHING_NOP))
as_fatal ("No valid nop.");
- /* At this point we know that we have a single 16-bit insn that has
- a matching nop. We have to assemble it and put it into the saved
+ /* At this point we know that we have a single 16-bit insn that has
+ a matching nop. We have to assemble it and put it into the saved
insn and fixup chain arrays. */
if (insn0iscopro)
{
char *errmsg;
mep_insn insn;
insn and fixup chain arrays. */
if (insn0iscopro)
{
char *errmsg;
mep_insn insn;
-
+
/* Move the insn and it's fixups to the second element of the
/* Move the insn and it's fixups to the second element of the
- saved insns arra
r
y and insert a 16 bit core nope into the
+ saved insns array and insert a 16 bit core nope into the
first element. */
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
&insn.fields, insn.buffer,
first element. */
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
&insn.fields, insn.buffer,
@@
-672,7
+670,7
@@
mep_check_parallel32_scheduling (void)
/* Move the insn in element 0 to element 1 and insert the
nop into element 0. Move the fixups in element 0 to
/* Move the insn in element 0 to element 1 and insert the
nop into element 0. Move the fixups in element 0 to
- element 1 and save the current fixups to element 0.
+ element 1 and save the current fixups to element 0.
Really there aren't any fixups at this point because we're
inserting a nop but we might as well be general so that
if there's ever a need to insert a general insn, we'll
Really there aren't any fixups at this point because we're
inserting a nop but we might as well be general so that
if there's ever a need to insert a general insn, we'll
@@
-760,7
+758,7
@@
mep_check_parallel64_scheduling (void)
1. The instruction is a 64 bit coprocessor insn and can be
executed by itself. Valid.
1. The instruction is a 64 bit coprocessor insn and can be
executed by itself. Valid.
- 2. The instrucion is a core instruction for which a cop nop
+ 2. The instruc
t
ion is a core instruction for which a cop nop
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
@@
-775,7
+773,7
@@
mep_check_parallel64_scheduling (void)
we have to abort. */
/* If the insn is 64 bits long, it can run alone. The size check
we have to abort. */
/* If the insn is 64 bits long, it can run alone. The size check
- is done indepe
penda
ntly of whether the insn is core or copro
+ is done indepe
nde
ntly of whether the insn is core or copro
in case 64 bit coprocessor insns are added later. */
if (insn0length == 64)
return;
in case 64 bit coprocessor insns are added later. */
if (insn0length == 64)
return;
@@
-819,7
+817,7
@@
mep_check_parallel64_scheduling (void)
nop has been added, then make the necessary changes and
handle its assembly and insertion here. Otherwise,
go figure out why either:
nop has been added, then make the necessary changes and
handle its assembly and insertion here. Otherwise,
go figure out why either:
-
+
1. The assembler thinks that there is a 32-bit core nop
to match a 32-bit coprocessor insn, or
2. The assembler thinks that there is a 48-bit core nop
1. The assembler thinks that there is a 32-bit core nop
to match a 32-bit coprocessor insn, or
2. The assembler thinks that there is a 48-bit core nop
@@
-836,7
+834,7
@@
mep_check_parallel64_scheduling (void)
/* Move the insn in element 0 to element 1 and insert the
nop into element 0. Move the fixups in element 0 to
/* Move the insn in element 0 to element 1 and insert the
nop into element 0. Move the fixups in element 0 to
- element 1 and save the current fixups to element 0.
+ element 1 and save the current fixups to element 0.
Really there aren't any fixups at this point because we're
inserting a nop but we might as well be general so that
if there's ever a need to insert a general insn, we'll
Really there aren't any fixups at this point because we're
inserting a nop but we might as well be general so that
if there's ever a need to insert a general insn, we'll
@@
-1113,7
+1111,7
@@
mep_check_ivc2_scheduling (void)
#if CGEN_INT_INSN_P
cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) temp, 32,
#if CGEN_INT_INSN_P
cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) temp, 32,
- m->buffer[0]);
+ m->buffer[0]
, gas_cgen_cpu_desc->insn_endian
);
#else
memcpy (temp, m->buffer, byte_len);
#endif
#else
memcpy (temp, m->buffer, byte_len);
#endif
@@
-1147,15
+1145,15
@@
mep_check_ivc2_scheduling (void)
#endif /* MEP_IVC2_SUPPORTED */
/* The scheduling functions are just filters for invalid combinations.
#endif /* MEP_IVC2_SUPPORTED */
/* The scheduling functions are just filters for invalid combinations.
- If there is a violation, they terminate assembly. Otherise they
- just fall through. Succesful combinations cause no side effects
+ If there is a violation, they terminate assembly. Other
w
ise they
+ just fall through. Succes
s
ful combinations cause no side effects
other than valid nop insertion. */
static void
mep_check_parallel_scheduling (void)
{
/* This is where we will eventually read the config information
other than valid nop insertion. */
static void
mep_check_parallel_scheduling (void)
{
/* This is where we will eventually read the config information
- and choose which scheduling checking function to call. */
+ and choose which scheduling checking function to call. */
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2)
mep_check_ivc2_scheduling ();
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2)
mep_check_ivc2_scheduling ();
@@
-1221,7
+1219,7
@@
md_assemble (char * str)
+ copro insn
We want to handle the general case where more than
+ copro insn
We want to handle the general case where more than
- one instruction can be prece
e
ded by a +. This will
+ one instruction can be preceded by a +. This will
happen later if we add support for internally parallel
coprocessors. We'll make the parsing nice and general
so that it can handle an arbitrary number of insns
happen later if we add support for internally parallel
coprocessors. We'll make the parsing nice and general
so that it can handle an arbitrary number of insns
@@
-1245,9
+1243,9
@@
md_assemble (char * str)
int thisInsnIsCopro = 0;
mep_insn insn;
int i;
int thisInsnIsCopro = 0;
mep_insn insn;
int i;
-
+
/* Initialize the insn buffer */
/* Initialize the insn buffer */
-
+
if (! CGEN_INT_INSN_P)
for (i=0; i < CGEN_MAX_INSN_SIZE; i++)
insn.buffer[i]='\0';
if (! CGEN_INT_INSN_P)
for (i=0; i < CGEN_MAX_INSN_SIZE; i++)
insn.buffer[i]='\0';
@@
-1301,7
+1299,7
@@
md_assemble (char * str)
/* Check for a + with a core insn and abort if found. */
if (!thisInsnIsCopro)
{
/* Check for a + with a core insn and abort if found. */
if (!thisInsnIsCopro)
{
- as_fatal("A core insn cannot be prece
e
ded by a +.\n");
+ as_fatal("A core insn cannot be preceded by a +.\n");
return;
}
return;
}
@@
-1382,8
+1380,8
@@
md_assemble (char * str)
valueT
md_section_align (segT segment, valueT size)
{
valueT
md_section_align (segT segment, valueT size)
{
- int align = bfd_
get_section_alignment (stdoutput,
segment);
- return ((size + (1 << align) - 1) &
(-
1 << align));
+ int align = bfd_
section_alignment (
segment);
+ return ((size + (1 << align) - 1) &
-(
1 << align));
}
}
@@
-1530,7
+1528,7
@@
md_estimate_size_before_relax (fragS * fragP, segT segment)
|| S_IS_WEAK (fragP->fr_symbol)
#ifdef MEP_IVC2_SUPPORTED
|| (mep_cop == EF_MEP_COP_IVC2
|| S_IS_WEAK (fragP->fr_symbol)
#ifdef MEP_IVC2_SUPPORTED
|| (mep_cop == EF_MEP_COP_IVC2
- && bfd_
get_section_flags (stdoutput,
segment) & SEC_MEP_VLIW)
+ && bfd_
section_flags (
segment) & SEC_MEP_VLIW)
#endif /* MEP_IVC2_SUPPORTED */
)
{
#endif /* MEP_IVC2_SUPPORTED */
)
{
@@
-1541,13
+1539,13
@@
md_estimate_size_before_relax (fragS * fragP, segT segment)
}
if (MEP_VLIW && ! MEP_VLIW64
}
if (MEP_VLIW && ! MEP_VLIW64
- && (bfd_
get_section_flags (stdoutput,
segment) & SEC_MEP_VLIW))
+ && (bfd_
section_flags (
segment) & SEC_MEP_VLIW))
{
/* Use 32 bit branches for vliw32 so the vliw word is not split. */
switch (fragP->fr_cgen.insn->base->num)
{
case MEP_INSN_BSR12:
{
/* Use 32 bit branches for vliw32 so the vliw word is not split. */
switch (fragP->fr_cgen.insn->base->num)
{
case MEP_INSN_BSR12:
- fragP->fr_subtype = insn_to_subtype
+ fragP->fr_subtype = insn_to_subtype
(subtype_mappings[fragP->fr_subtype].insn_for_extern);
break;
case MEP_INSN_BEQZ:
(subtype_mappings[fragP->fr_subtype].insn_for_extern);
break;
case MEP_INSN_BEQZ:
@@
-1574,7
+1572,7
@@
md_estimate_size_before_relax (fragS * fragP, segT segment)
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2
- && bfd_
get_section_flags (stdoutput,
segment) & SEC_MEP_VLIW)
+ && bfd_
section_flags (
segment) & SEC_MEP_VLIW)
return 0;
#endif /* MEP_IVC2_SUPPORTED */
return 0;
#endif /* MEP_IVC2_SUPPORTED */
@@
-1589,7
+1587,7
@@
mep_relax_frag (segT segment, fragS *fragP, long stretch)
long rv = relax_frag (segment, fragP, stretch);
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2
long rv = relax_frag (segment, fragP, stretch);
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2
- && bfd_
get_section_flags (stdoutput,
segment) & SEC_MEP_VLIW)
+ && bfd_
section_flags (
segment) & SEC_MEP_VLIW)
return 0;
#endif
return rv;
return 0;
#endif
return rv;
@@
-1615,7
+1613,7
@@
target_address_for (fragS *frag)
}
void
}
void
-md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
segT seg ATTRIBUTE_UNUSED,
fragS *fragP)
{
segT seg ATTRIBUTE_UNUSED,
fragS *fragP)
{
@@
-1626,7
+1624,7
@@
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
int core_mode;
#ifdef MEP_IVC2_SUPPORTED
int core_mode;
#ifdef MEP_IVC2_SUPPORTED
- if (bfd_
get_section_flags (stdoutput,
seg) & SEC_MEP_VLIW
+ if (bfd_
section_flags (
seg) & SEC_MEP_VLIW
&& mep_cop == EF_MEP_COP_IVC2)
core_mode = 0;
else
&& mep_cop == EF_MEP_COP_IVC2)
core_mode = 0;
else
@@
-1710,7
+1708,7
@@
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
operand = MEP_OPERAND_PCREL17A2;
break;
}
operand = MEP_OPERAND_PCREL17A2;
break;
}
- /*
...FALLTHROUGH...
*/
+ /*
Fall through.
*/
case MEP_INSN_JMP:
addend = target_address_for (fragP);
case MEP_INSN_JMP:
addend = target_address_for (fragP);
@@
-1725,6
+1723,7
@@
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
case MEP_INSN_BNEZ:
bit = 1;
case MEP_INSN_BNEZ:
bit = 1;
+ /* Fall through. */
case MEP_INSN_BEQZ:
fragP->fr_opcode[1^e] = bit | (addend & 0xfe);
operand = MEP_OPERAND_PCREL8A2;
case MEP_INSN_BEQZ:
fragP->fr_opcode[1^e] = bit | (addend & 0xfe);
operand = MEP_OPERAND_PCREL8A2;
@@
-1732,6
+1731,7
@@
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
case MEP_INSN_BNEI:
bit = 4;
case MEP_INSN_BNEI:
bit = 4;
+ /* Fall through. */
case MEP_INSN_BEQI:
if (subtype_mappings[fragP->fr_subtype].growth)
{
case MEP_INSN_BEQI:
if (subtype_mappings[fragP->fr_subtype].growth)
{
@@
-1790,7
+1790,7
@@
mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
switch (fixP->fx_cgen.opinfo)
{
case BFD_RELOC_MEP_LOW16:
switch (fixP->fx_cgen.opinfo)
{
case BFD_RELOC_MEP_LOW16:
- *valP = ((
long)(*valP & 0xffff)) << 16 >> 16
;
+ *valP = ((
*valP & 0xffff) ^ 0x8000) - 0x8000
;
break;
case BFD_RELOC_MEP_HI16U:
*valP >>= 16;
break;
case BFD_RELOC_MEP_HI16U:
*valP >>= 16;
@@
-1800,7
+1800,7
@@
mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
break;
}
break;
}
- /* Now call cgen's md_aply_fix. */
+ /* Now call cgen's md_ap
p
ly_fix. */
gas_cgen_md_apply_fix (fixP, valP, seg);
}
gas_cgen_md_apply_fix (fixP, valP, seg);
}
@@
-1867,7
+1867,7
@@
md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
#ifdef OBJ_COMPLEX_RELC
/* coalescing this into RELOC_MEP_16 is actually a bug,
since it's a signed operand. let the relc code handle it. */
#ifdef OBJ_COMPLEX_RELC
/* coalescing this into RELOC_MEP_16 is actually a bug,
since it's a signed operand. let the relc code handle it. */
- return BFD_RELOC_RELC;
+ return BFD_RELOC_RELC;
#endif
case MEP_OPERAND_UIMM16:
#endif
case MEP_OPERAND_UIMM16:
@@
-1880,7
+1880,7
@@
md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
default:
#ifdef OBJ_COMPLEX_RELC
default:
#ifdef OBJ_COMPLEX_RELC
- /* this is not an error, yet.
+ /* this is not an error, yet.
pass it to the linker. */
return BFD_RELOC_RELC;
#endif
pass it to the linker. */
return BFD_RELOC_RELC;
#endif
@@
-1935,7
+1935,7
@@
mep_cgen_record_fixup_exp (fragS *frag,
tc_gen_reloc. */
void
tc_gen_reloc. */
void
-mep_frob_file ()
+mep_frob_file (
void
)
{
struct mep_hi_fixup * l;
{
struct mep_hi_fixup * l;
@@
-2040,7
+2040,7
@@
md_number_to_chars (char *buf, valueT val, int n)
number_to_chars_littleendian (buf, val, n);
}
number_to_chars_littleendian (buf, val, n);
}
-char *
+c
onst c
har *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
@@
-2081,7
+2081,7
@@
mep_fix_adjustable (fixS *fixP)
}
bfd_vma
}
bfd_vma
-mep_elf_section_letter (int letter, char **ptrmsg)
+mep_elf_section_letter (int letter, c
onst c
har **ptrmsg)
{
if (letter == 'v')
return SHF_MEP_VLIW;
{
if (letter == 'v')
return SHF_MEP_VLIW;
@@
-2110,7
+2110,7
@@
mep_vtext_section (void)
{
flagword applicable = bfd_applicable_section_flags (stdoutput);
vtext_section = subseg_new (VTEXT_SECTION_NAME, 0);
{
flagword applicable = bfd_applicable_section_flags (stdoutput);
vtext_section = subseg_new (VTEXT_SECTION_NAME, 0);
- bfd_set_section_flags (
stdoutput,
vtext_section,
+ bfd_set_section_flags (vtext_section,
applicable & (SEC_ALLOC | SEC_LOAD | SEC_RELOC
| SEC_CODE | SEC_READONLY
| SEC_MEP_VLIW));
applicable & (SEC_ALLOC | SEC_LOAD | SEC_RELOC
| SEC_CODE | SEC_READONLY
| SEC_MEP_VLIW));
@@
-2185,7
+2185,7
@@
mep_cleanup (void)
{
/* Take care of any insns left to be parallelized when the file ends.
This is mainly here to handle the case where the file ends with an
{
/* Take care of any insns left to be parallelized when the file ends.
This is mainly here to handle the case where the file ends with an
- insn prece
e
ded by a + or the file ends unexpectedly. */
+ insn preceded by a + or the file ends unexpectedly. */
if (mode == VLIW)
mep_process_saved_insns ();
}
if (mode == VLIW)
mep_process_saved_insns ();
}
@@
-2199,5
+2199,5
@@
mep_flush_pending_output (void)
pluspresent = 0;
}
pluspresent = 0;
}
- return 1;
+ return 1;
}
}
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