+ if (vinsn->num_slots
+ != xtensa_format_num_slots (xtensa_default_isa, vinsn->format))
+ {
+ as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
+ xtensa_format_name (xtensa_default_isa, vinsn->format),
+ xtensa_format_num_slots (xtensa_default_isa, vinsn->format),
+ vinsn->num_slots);
+ xg_clear_vinsn (vinsn);
+ return;
+ }
+
+ if (resources_conflict (vinsn))
+ {
+ as_where (&file_name, &line);
+ as_bad_where (file_name, line, _("illegal resource usage in bundle"));
+ fprintf (stderr, " ops were: ");
+ for (i = 0; i < vinsn->num_slots; i++)
+ fprintf (stderr, " %s;",
+ xtensa_opcode_name (xtensa_default_isa,
+ vinsn->slots[i].opcode));
+ fprintf (stderr, "\n");
+ xg_clear_vinsn (vinsn);
+ return;
+ }
+
+ for (i = 0; i < vinsn->num_slots; i++)
+ {
+ if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
+ {
+ symbolS *lit_sym = NULL;
+ int j;
+ bfd_boolean e = FALSE;
+ bfd_boolean saved_density = density_supported;
+
+ /* We don't want to narrow ops inside multi-slot bundles. */
+ if (vinsn->num_slots > 1)
+ density_supported = FALSE;
+
+ istack_init (&slotstack);
+ if (vinsn->slots[i].opcode == xtensa_nop_opcode)
+ {
+ vinsn->slots[i].opcode =
+ xtensa_format_slot_nop_opcode (xtensa_default_isa,
+ vinsn->format, i);
+ vinsn->slots[i].ntok = 0;
+ }
+
+ if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
+ {
+ e = TRUE;
+ continue;
+ }
+
+ density_supported = saved_density;
+
+ if (e)
+ {
+ xg_clear_vinsn (vinsn);
+ return;
+ }
+
+ for (j = 0; j < slotstack.ninsn; j++)
+ {
+ TInsn *insn = &slotstack.insn[j];
+ if (insn->insn_type == ITYPE_LITERAL)
+ {
+ assert (lit_sym == NULL);
+ lit_sym = xg_assemble_literal (insn);
+ }
+ else
+ {
+ assert (insn->insn_type == ITYPE_INSN);
+ if (lit_sym)
+ xg_resolve_literals (insn, lit_sym);
+ if (j != slotstack.ninsn - 1)
+ emit_single_op (insn);
+ }
+ }
+
+ if (vinsn->num_slots > 1)
+ {
+ if (opcode_fits_format_slot
+ (slotstack.insn[slotstack.ninsn - 1].opcode,
+ vinsn->format, i))
+ {
+ vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
+ }
+ else
+ {
+ emit_single_op (&slotstack.insn[slotstack.ninsn - 1]);
+ if (vinsn->format == XTENSA_UNDEFINED)
+ vinsn->slots[i].opcode = xtensa_nop_opcode;
+ else
+ vinsn->slots[i].opcode
+ = xtensa_format_slot_nop_opcode (xtensa_default_isa,
+ vinsn->format, i);
+
+ vinsn->slots[i].ntok = 0;
+ }
+ }
+ else
+ {
+ vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
+ vinsn->format = XTENSA_UNDEFINED;
+ }
+ }
+ }
+
+ /* Now check resource conflicts on the modified bundle. */
+ if (resources_conflict (vinsn))
+ {
+ as_where (&file_name, &line);
+ as_bad_where (file_name, line, _("illegal resource usage in bundle"));
+ fprintf (stderr, " ops were: ");
+ for (i = 0; i < vinsn->num_slots; i++)
+ fprintf (stderr, " %s;",
+ xtensa_opcode_name (xtensa_default_isa,
+ vinsn->slots[i].opcode));
+ fprintf (stderr, "\n");
+ xg_clear_vinsn (vinsn);
+ return;
+ }
+
+ /* First, find a format that works. */
+ if (vinsn->format == XTENSA_UNDEFINED)
+ vinsn->format = xg_find_narrowest_format (vinsn);
+
+ xg_assemble_vliw_tokens (vinsn);
+
+ xg_clear_vinsn (vinsn);
+}
+
+
+/* Given an vliw instruction, what conflicts are there in register
+ usage and in writes to states and queues?
+
+ This function does two things:
+ 1. Reports an error when a vinsn contains illegal combinations
+ of writes to registers states or queues.
+ 2. Marks individual tinsns as not relaxable if the combination
+ contains antidependencies.
+
+ Job 2 handles things like swap semantics in instructions that need
+ to be relaxed. For example,
+
+ addi a0, a1, 100000
+
+ normally would be relaxed to
+
+ l32r a0, some_label
+ add a0, a1, a0
+
+ _but_, if the above instruction is bundled with an a0 reader, e.g.,
+
+ { addi a0, a1, 10000 ; add a2, a0, a4 ; }
+
+ then we can't relax it into
+
+ l32r a0, some_label
+ { add a0, a1, a0 ; add a2, a0, a4 ; }
+
+ because the value of a0 is trashed before the second add can read it. */
+
+static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
+
+static bfd_boolean
+find_vinsn_conflicts (vliw_insn *vinsn)
+{
+ int i, j;
+ int branches = 0;
+ xtensa_isa isa = xtensa_default_isa;
+
+ assert (!past_xtensa_end);
+
+ for (i = 0 ; i < vinsn->num_slots; i++)
+ {
+ TInsn *op1 = &vinsn->slots[i];
+ if (op1->is_specific_opcode)
+ op1->keep_wide = TRUE;
+ else
+ op1->keep_wide = FALSE;
+ }
+
+ for (i = 0 ; i < vinsn->num_slots; i++)
+ {
+ TInsn *op1 = &vinsn->slots[i];
+
+ if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
+ branches++;
+
+ for (j = 0; j < vinsn->num_slots; j++)
+ {
+ if (i != j)
+ {
+ TInsn *op2 = &vinsn->slots[j];
+ char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
+ switch (conflict_type)
+ {
+ case 'c':
+ as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
+ xtensa_opcode_name (isa, op1->opcode), i,
+ xtensa_opcode_name (isa, op2->opcode), j);
+ return TRUE;
+ case 'd':
+ as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
+ xtensa_opcode_name (isa, op1->opcode), i,
+ xtensa_opcode_name (isa, op2->opcode), j);
+ return TRUE;
+ case 'e':
+ as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
+ xtensa_opcode_name (isa, op1->opcode), i,
+ xtensa_opcode_name (isa, op2->opcode), j);
+ return TRUE;
+ case 'f':
+ as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
+ xtensa_opcode_name (isa, op1->opcode), i,
+ xtensa_opcode_name (isa, op2->opcode), j);
+ return TRUE;
+ default:
+ /* Everything is OK. */
+ break;
+ }
+ op2->is_specific_opcode = (op2->is_specific_opcode
+ || conflict_type == 'a');
+ }
+ }
+ }
+
+ if (branches > 1)
+ {
+ as_bad (_("multiple branches or jumps in the same bundle"));
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+
+/* Check how the state used by t1 and t2 relate.
+ Cases found are:
+
+ case A: t1 reads a register t2 writes (an antidependency within a bundle)
+ case B: no relationship between what is read and written (both could
+ read the same reg though)
+ case C: t1 writes a register t2 writes (a register conflict within a
+ bundle)
+ case D: t1 writes a state that t2 also writes
+ case E: t1 writes a tie queue that t2 also writes
+ case F: two volatile queue accesses
+*/
+
+static char
+check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
+{
+ xtensa_isa isa = xtensa_default_isa;
+ xtensa_regfile t1_regfile, t2_regfile;
+ int t1_reg, t2_reg;
+ int t1_base_reg, t1_last_reg;
+ int t2_base_reg, t2_last_reg;
+ char t1_inout, t2_inout;
+ int i, j;
+ char conflict = 'b';
+ int t1_states;
+ int t2_states;
+ int t1_interfaces;
+ int t2_interfaces;
+ bfd_boolean t1_volatile = FALSE;
+ bfd_boolean t2_volatile = FALSE;
+
+ /* Check registers. */
+ for (j = 0; j < t2->ntok; j++)
+ {
+ if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
+ continue;
+
+ t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
+ t2_base_reg = t2->tok[j].X_add_number;
+ t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
+
+ for (i = 0; i < t1->ntok; i++)
+ {
+ if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
+ continue;
+
+ t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
+
+ if (t1_regfile != t2_regfile)
+ continue;
+
+ t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
+ t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
+
+ if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
+ || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
+ {
+ if (t1_inout == 'm' || t1_inout == 'o'
+ || t2_inout == 'm' || t2_inout == 'o')
+ {
+ conflict = 'a';
+ continue;
+ }
+ }
+
+ t1_base_reg = t1->tok[i].X_add_number;
+ t1_last_reg = (t1_base_reg
+ + xtensa_operand_num_regs (isa, t1->opcode, i));
+
+ for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
+ {
+ for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
+ {
+ if (t1_reg != t2_reg)
+ continue;
+
+ if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
+ {
+ conflict = 'a';
+ continue;
+ }
+
+ if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
+ {
+ conflict = 'a';
+ continue;
+ }
+
+ if (t1_inout != 'i' && t2_inout != 'i')
+ return 'c';
+ }
+ }
+ }
+ }
+
+ /* Check states. */
+ t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
+ t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
+ for (j = 0; j < t2_states; j++)
+ {
+ xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
+ t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
+ for (i = 0; i < t1_states; i++)
+ {
+ xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
+ t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
+ if (t1_so != t2_so)
+ continue;
+
+ if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
+ {
+ conflict = 'a';
+ continue;
+ }
+
+ if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
+ {
+ conflict = 'a';
+ continue;
+ }
+
+ if (t1_inout != 'i' && t2_inout != 'i')
+ return 'd';
+ }
+ }
+
+ /* Check tieports. */
+ t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
+ t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
+ for (j = 0; j < t2_interfaces; j++)
+ {
+ xtensa_interface t2_int
+ = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
+ int t2_class = xtensa_interface_class_id (isa, t2_int);
+
+ t2_inout = xtensa_interface_inout (isa, t2_int);
+ if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
+ t2_volatile = TRUE;
+
+ for (i = 0; i < t1_interfaces; i++)
+ {
+ xtensa_interface t1_int
+ = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
+ int t1_class = xtensa_interface_class_id (isa, t1_int);
+
+ t1_inout = xtensa_interface_inout (isa, t1_int);
+ if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
+ t1_volatile = TRUE;
+
+ if (t1_volatile && t2_volatile && (t1_class == t2_class))
+ return 'f';
+
+ if (t1_int != t2_int)
+ continue;
+
+ if (t2_inout == 'i' && t1_inout == 'o')
+ {
+ conflict = 'a';
+ continue;
+ }
+
+ if (t1_inout == 'i' && t2_inout == 'o')
+ {
+ conflict = 'a';
+ continue;
+ }
+
+ if (t1_inout != 'i' && t2_inout != 'i')
+ return 'e';
+ }
+ }
+
+ return conflict;
+}
+
+
+static xtensa_format
+xg_find_narrowest_format (vliw_insn *vinsn)
+{
+ /* Right now we assume that the ops within the vinsn are properly
+ ordered for the slots that the programmer wanted them in. In
+ other words, we don't rearrange the ops in hopes of finding a
+ better format. The scheduler handles that. */
+
+ xtensa_isa isa = xtensa_default_isa;
+ xtensa_format format;
+ vliw_insn v_copy = *vinsn;
+ xtensa_opcode nop_opcode = xtensa_nop_opcode;
+
+ if (vinsn->num_slots == 1)
+ return xg_get_single_format (vinsn->slots[0].opcode);
+
+ for (format = 0; format < xtensa_isa_num_formats (isa); format++)
+ {
+ v_copy = *vinsn;
+ if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
+ {
+ int slot;
+ int fit = 0;
+ for (slot = 0; slot < v_copy.num_slots; slot++)
+ {
+ if (v_copy.slots[slot].opcode == nop_opcode)
+ {
+ v_copy.slots[slot].opcode =
+ xtensa_format_slot_nop_opcode (isa, format, slot);
+ v_copy.slots[slot].ntok = 0;
+ }
+
+ if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
+ format, slot))
+ fit++;
+ else if (v_copy.num_slots > 1)
+ {
+ TInsn widened;
+ /* Try the widened version. */
+ if (!v_copy.slots[slot].keep_wide
+ && !v_copy.slots[slot].is_specific_opcode
+ && xg_is_single_relaxable_insn (&v_copy.slots[slot],
+ &widened, TRUE)
+ && opcode_fits_format_slot (widened.opcode,
+ format, slot))
+ {
+ v_copy.slots[slot] = widened;
+ fit++;
+ }
+ }
+ }
+ if (fit == v_copy.num_slots)
+ {
+ *vinsn = v_copy;
+ xtensa_format_encode (isa, format, vinsn->insnbuf);
+ vinsn->format = format;
+ break;
+ }
+ }
+ }
+
+ if (format == xtensa_isa_num_formats (isa))
+ return XTENSA_UNDEFINED;
+
+ return format;
+}
+
+
+/* Return the additional space needed in a frag
+ for possible relaxations of any ops in a VLIW insn.
+ Also fill out the relaxations that might be required of
+ each tinsn in the vinsn. */
+
+static int
+relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag)
+{
+ bfd_boolean finish_frag = FALSE;
+ int extra_space = 0;
+ int slot;
+
+ for (slot = 0; slot < vinsn->num_slots; slot++)
+ {
+ TInsn *tinsn = &vinsn->slots[slot];
+ if (!tinsn_has_symbolic_operands (tinsn))
+ {
+ /* A narrow instruction could be widened later to help
+ alignment issues. */
+ if (xg_is_single_relaxable_insn (tinsn, 0, TRUE)
+ && !tinsn->is_specific_opcode
+ && vinsn->num_slots == 1)
+ {
+ /* Difference in bytes between narrow and wide insns... */
+ extra_space += 1;
+ tinsn->subtype = RELAX_NARROW;
+ }
+ }
+ else
+ {
+ if (workaround_b_j_loop_end
+ && tinsn->opcode == xtensa_jx_opcode
+ && use_transform ())
+ {
+ /* Add 2 of these. */
+ extra_space += 3; /* for the nop size */
+ tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
+ }
+
+ /* Need to assemble it with space for the relocation. */
+ if (xg_is_relaxable_insn (tinsn, 0)
+ && !tinsn->is_specific_opcode)
+ {
+ int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
+ int max_literal_size =
+ xg_get_max_insn_widen_literal_size (tinsn->opcode);
+
+ tinsn->literal_space = max_literal_size;
+
+ tinsn->subtype = RELAX_IMMED;
+ extra_space += max_size;
+ }
+ else
+ {
+ /* A fix record will be added for this instruction prior
+ to relaxation, so make it end the frag. */
+ finish_frag = TRUE;
+ }
+ }
+ }
+ *pfinish_frag = finish_frag;
+ return extra_space;
+}
+
+
+static void
+bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn)
+{
+ xtensa_isa isa = xtensa_default_isa;
+ int slot, chosen_slot;
+
+ vinsn->format = xg_get_single_format (tinsn->opcode);
+ assert (vinsn->format != XTENSA_UNDEFINED);
+ vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format);
+
+ chosen_slot = xg_get_single_slot (tinsn->opcode);
+ for (slot = 0; slot < vinsn->num_slots; slot++)
+ {
+ if (slot == chosen_slot)
+ vinsn->slots[slot] = *tinsn;
+ else
+ {
+ vinsn->slots[slot].opcode =
+ xtensa_format_slot_nop_opcode (isa, vinsn->format, slot);
+ vinsn->slots[slot].ntok = 0;
+ vinsn->slots[slot].insn_type = ITYPE_INSN;
+ }
+ }
+}
+
+
+static bfd_boolean
+emit_single_op (TInsn *orig_insn)
+{
+ int i;
+ IStack istack; /* put instructions into here */
+ symbolS *lit_sym = NULL;
+ symbolS *label_sym = NULL;
+
+ istack_init (&istack);
+
+ /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
+ Because the scheduling and bundling characteristics of movi and
+ l32r or const16 are so different, we can do much better if we relax
+ it prior to scheduling and bundling, rather than after. */
+ if ((orig_insn->opcode == xtensa_movi_opcode
+ || orig_insn->opcode == xtensa_movi_n_opcode)
+ && !cur_vinsn.inside_bundle
+ && (orig_insn->tok[1].X_op == O_symbol
+ || orig_insn->tok[1].X_op == O_pltrel))
+ xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
+ else
+ if (xg_expand_assembly_insn (&istack, orig_insn))
+ return TRUE;
+
+ for (i = 0; i < istack.ninsn; i++)
+ {
+ TInsn *insn = &istack.insn[i];
+ switch (insn->insn_type)
+ {
+ case ITYPE_LITERAL:
+ assert (lit_sym == NULL);
+ lit_sym = xg_assemble_literal (insn);
+ break;
+ case ITYPE_LABEL:
+ {
+ static int relaxed_sym_idx = 0;
+ char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12);
+ sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
+ colon (label);
+ assert (label_sym == NULL);
+ label_sym = symbol_find_or_make (label);
+ assert (label_sym);
+ free (label);
+ }
+ break;
+ case ITYPE_INSN:
+ {
+ vliw_insn v;
+ if (lit_sym)
+ xg_resolve_literals (insn, lit_sym);
+ if (label_sym)
+ xg_resolve_labels (insn, label_sym);
+ xg_init_vinsn (&v);
+ bundle_tinsn (insn, &v);
+ finish_vinsn (&v);
+ xg_free_vinsn (&v);
+ }
+ break;
+ default:
+ assert (0);
+ break;
+ }
+ }
+ return FALSE;
+}
+
+
+static int
+total_frag_text_expansion (fragS *fragP)
+{
+ int slot;
+ int total_expansion = 0;
+
+ for (slot = 0; slot < MAX_SLOTS; slot++)
+ total_expansion += fragP->tc_frag_data.text_expansion[slot];
+
+ return total_expansion;
+}
+
+
+/* Emit a vliw instruction to the current fragment. */
+
+static void
+xg_assemble_vliw_tokens (vliw_insn *vinsn)
+{
+ bfd_boolean finish_frag;
+ bfd_boolean is_jump = FALSE;
+ bfd_boolean is_branch = FALSE;
+ xtensa_isa isa = xtensa_default_isa;
+ int i;
+ int insn_size;
+ int extra_space;
+ char *f = NULL;
+ int slot;
+ unsigned current_line, best_linenum;
+ char *current_file;
+
+ best_linenum = UINT_MAX;
+
+ if (generating_literals)
+ {
+ static int reported = 0;
+ if (reported < 4)
+ as_bad_where (frag_now->fr_file, frag_now->fr_line,
+ _("cannot assemble into a literal fragment"));
+ if (reported == 3)
+ as_bad (_("..."));
+ reported++;
+ return;
+ }
+
+ if (frag_now_fix () != 0
+ && (! frag_now->tc_frag_data.is_insn
+ || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
+ || !use_transform () != frag_now->tc_frag_data.is_no_transform
+ || (directive_state[directive_longcalls]
+ != frag_now->tc_frag_data.use_longcalls)
+ || (directive_state[directive_absolute_literals]
+ != frag_now->tc_frag_data.use_absolute_literals)))
+ {
+ frag_wane (frag_now);
+ frag_new (0);
+ xtensa_set_frag_assembly_state (frag_now);
+ }
+
+ if (workaround_a0_b_retw
+ && vinsn->num_slots == 1
+ && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
+ && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
+ && use_transform ())
+ {
+ has_a0_b_retw = TRUE;
+
+ /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
+ After the first assembly pass we will check all of them and
+ add a nop if needed. */
+ frag_now->tc_frag_data.is_insn = TRUE;
+ frag_var (rs_machine_dependent, 4, 4,
+ RELAX_ADD_NOP_IF_A0_B_RETW,
+ frag_now->fr_symbol,
+ frag_now->fr_offset,
+ NULL);
+ xtensa_set_frag_assembly_state (frag_now);
+ frag_now->tc_frag_data.is_insn = TRUE;
+ frag_var (rs_machine_dependent, 4, 4,
+ RELAX_ADD_NOP_IF_A0_B_RETW,
+ frag_now->fr_symbol,
+ frag_now->fr_offset,
+ NULL);
+ xtensa_set_frag_assembly_state (frag_now);
+ }
+
+ for (i = 0; i < vinsn->num_slots; i++)
+ {
+ /* See if the instruction implies an aligned section. */
+ if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1)
+ record_alignment (now_seg, 2);
+
+ /* Also determine the best line number for debug info. */
+ best_linenum = vinsn->slots[i].linenum < best_linenum
+ ? vinsn->slots[i].linenum : best_linenum;
+ }
+
+ /* Special cases for instructions that force an alignment... */
+ /* None of these opcodes are bundle-able. */
+ if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
+ {
+ int max_fill;
+
+ xtensa_set_frag_assembly_state (frag_now);
+ frag_now->tc_frag_data.is_insn = TRUE;
+
+ max_fill = get_text_align_max_fill_size
+ (get_text_align_power (xtensa_fetch_width),
+ TRUE, frag_now->tc_frag_data.is_no_density);
+
+ if (use_transform ())
+ frag_var (rs_machine_dependent, max_fill, max_fill,
+ RELAX_ALIGN_NEXT_OPCODE,
+ frag_now->fr_symbol,
+ frag_now->fr_offset,
+ NULL);
+ else
+ frag_var (rs_machine_dependent, 0, 0,
+ RELAX_CHECK_ALIGN_NEXT_OPCODE, 0, 0, NULL);
+ xtensa_set_frag_assembly_state (frag_now);
+
+ xtensa_move_labels (frag_now, 0, FALSE);
+ }
+
+ if (vinsn->slots[0].opcode == xtensa_entry_opcode
+ && !vinsn->slots[0].is_specific_opcode)
+ {
+ xtensa_mark_literal_pool_location ();
+ xtensa_move_labels (frag_now, 0, TRUE);
+ frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
+ }
+
+ if (vinsn->num_slots == 1)
+ {
+ if (workaround_a0_b_retw && use_transform ())
+ set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
+ is_register_writer (&vinsn->slots[0], "a", 0));
+
+ set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
+ is_bad_loopend_opcode (&vinsn->slots[0]));
+ }
+ else
+ set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
+
+ insn_size = xtensa_format_length (isa, vinsn->format);
+
+ extra_space = relaxation_requirements (vinsn, &finish_frag);
+
+ /* vinsn_to_insnbuf will produce the error. */
+ if (vinsn->format != XTENSA_UNDEFINED)
+ {
+ f = frag_more (insn_size + extra_space);
+ xtensa_set_frag_assembly_state (frag_now);
+ frag_now->tc_frag_data.is_insn = TRUE;
+ }
+
+ vinsn_to_insnbuf (vinsn, f, frag_now, FALSE);
+ if (vinsn->format == XTENSA_UNDEFINED)
+ return;
+
+ xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0);
+
+ /* Temporarily set the logical line number to the one we want to appear
+ in the debug information. */
+ as_where (¤t_file, ¤t_line);
+ new_logical_line (current_file, best_linenum);
+ dwarf2_emit_insn (insn_size + extra_space);
+ new_logical_line (current_file, current_line);
+
+ for (slot = 0; slot < vinsn->num_slots; slot++)
+ {
+ TInsn *tinsn = &vinsn->slots[slot];
+ frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
+ frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
+ frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
+ frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
+ if (tinsn->literal_space != 0)
+ xg_assemble_literal_space (tinsn->literal_space, slot);
+
+ if (tinsn->subtype == RELAX_NARROW)
+ assert (vinsn->num_slots == 1);
+ if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
+ is_jump = TRUE;
+ if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
+ is_branch = TRUE;
+
+ if (tinsn->subtype || tinsn->symbol || tinsn->offset
+ || tinsn->literal_frag || is_jump || is_branch)
+ finish_frag = TRUE;
+ }
+
+ if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
+ frag_now->tc_frag_data.is_specific_opcode = TRUE;
+
+ if (finish_frag)
+ {
+ frag_variant (rs_machine_dependent,
+ extra_space, extra_space, RELAX_SLOTS,
+ frag_now->fr_symbol, frag_now->fr_offset, f);
+ xtensa_set_frag_assembly_state (frag_now);
+ }
+
+ /* Special cases for loops:
+ close_loop_end should be inserted AFTER short_loop.
+ Make sure that CLOSE loops are processed BEFORE short_loops
+ when converting them. */
+
+ /* "short_loop": Add a NOP if the loop is < 4 bytes. */
+ if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode)
+ && !vinsn->slots[0].is_specific_opcode)
+ {
+ if (workaround_short_loop && use_transform ())
+ {
+ maybe_has_short_loop = TRUE;
+ frag_now->tc_frag_data.is_insn = TRUE;
+ frag_var (rs_machine_dependent, 4, 4,
+ RELAX_ADD_NOP_IF_SHORT_LOOP,
+ frag_now->fr_symbol, frag_now->fr_offset, NULL);
+ frag_now->tc_frag_data.is_insn = TRUE;
+ frag_var (rs_machine_dependent, 4, 4,
+ RELAX_ADD_NOP_IF_SHORT_LOOP,
+ frag_now->fr_symbol, frag_now->fr_offset, NULL);
+ }
+
+ /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
+ loop at least 12 bytes away from another loop's end. */
+ if (workaround_close_loop_end && use_transform ())
+ {
+ maybe_has_close_loop_end = TRUE;
+ frag_now->tc_frag_data.is_insn = TRUE;
+ frag_var (rs_machine_dependent, 12, 12,
+ RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
+ frag_now->fr_symbol, frag_now->fr_offset, NULL);
+ }
+ }
+
+ if (use_transform ())
+ {
+ if (is_jump)
+ {
+ assert (finish_frag);
+ frag_var (rs_machine_dependent,
+ UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
+ RELAX_UNREACHABLE,
+ frag_now->fr_symbol, frag_now->fr_offset, NULL);
+ xtensa_set_frag_assembly_state (frag_now);
+ }
+ else if (is_branch && do_align_targets ())
+ {
+ assert (finish_frag);
+ frag_var (rs_machine_dependent,
+ UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
+ RELAX_MAYBE_UNREACHABLE,
+ frag_now->fr_symbol, frag_now->fr_offset, NULL);
+ xtensa_set_frag_assembly_state (frag_now);
+ frag_var (rs_machine_dependent,
+ 0, 0,
+ RELAX_MAYBE_DESIRE_ALIGN,
+ frag_now->fr_symbol, frag_now->fr_offset, NULL);
+ xtensa_set_frag_assembly_state (frag_now);
+ }
+ }
+
+ /* Now, if the original opcode was a call... */
+ if (do_align_targets ()
+ && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
+ {
+ float freq = get_subseg_total_freq (now_seg, now_subseg);
+ frag_now->tc_frag_data.is_insn = TRUE;
+ frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
+ frag_now->fr_symbol, frag_now->fr_offset, NULL);
+ xtensa_set_frag_assembly_state (frag_now);
+ }
+
+ if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
+ {
+ frag_wane (frag_now);
+ frag_new (0);
+ xtensa_set_frag_assembly_state (frag_now);
+ }
+}
+
+\f
+/* xtensa_end and helper functions. */
+
+static void xtensa_cleanup_align_frags (void);
+static void xtensa_fix_target_frags (void);
+static void xtensa_mark_narrow_branches (void);
+static void xtensa_mark_zcl_first_insns (void);
+static void xtensa_fix_a0_b_retw_frags (void);
+static void xtensa_fix_b_j_loop_end_frags (void);
+static void xtensa_fix_close_loop_end_frags (void);
+static void xtensa_fix_short_loop_frags (void);
+static void xtensa_sanity_check (void);
+
+void
+xtensa_end (void)
+{
+ directive_balance ();
+ xtensa_flush_pending_output ();
+
+ past_xtensa_end = TRUE;
+
+ xtensa_move_literals ();
+
+ xtensa_reorder_segments ();
+ xtensa_cleanup_align_frags ();
+ xtensa_fix_target_frags ();
+ if (workaround_a0_b_retw && has_a0_b_retw)
+ xtensa_fix_a0_b_retw_frags ();
+ if (workaround_b_j_loop_end)
+ xtensa_fix_b_j_loop_end_frags ();
+
+ /* "close_loop_end" should be processed BEFORE "short_loop". */
+ if (workaround_close_loop_end && maybe_has_close_loop_end)
+ xtensa_fix_close_loop_end_frags ();
+
+ if (workaround_short_loop && maybe_has_short_loop)
+ xtensa_fix_short_loop_frags ();
+ xtensa_mark_narrow_branches ();
+ xtensa_mark_zcl_first_insns ();
+
+ xtensa_sanity_check ();
+}
+
+
+static void
+xtensa_cleanup_align_frags (void)
+{
+ frchainS *frchP;
+
+ for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
+ {
+ fragS *fragP;
+ /* Walk over all of the fragments in a subsection. */
+ for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+ {
+ if ((fragP->fr_type == rs_align
+ || fragP->fr_type == rs_align_code
+ || (fragP->fr_type == rs_machine_dependent
+ && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
+ || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
+ && fragP->fr_fix == 0)
+ {
+ fragS *next = fragP->fr_next;
+
+ while (next
+ && next->fr_fix == 0
+ && next->fr_type == rs_machine_dependent
+ && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
+ {
+ frag_wane (next);
+ next = next->fr_next;
+ }
+ }
+ /* If we don't widen branch targets, then they
+ will be easier to align. */
+ if (fragP->tc_frag_data.is_branch_target
+ && fragP->fr_opcode == fragP->fr_literal
+ && fragP->fr_type == rs_machine_dependent
+ && fragP->fr_subtype == RELAX_SLOTS
+ && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
+ frag_wane (fragP);
+ if (fragP->fr_type == rs_machine_dependent
+ && fragP->fr_subtype == RELAX_UNREACHABLE)
+ fragP->tc_frag_data.is_unreachable = TRUE;
+ }
+ }
+}
+
+
+/* Re-process all of the fragments looking to convert all of the
+ RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
+ target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
+ Otherwise, convert to a .fill 0. */
+
+static void
+xtensa_fix_target_frags (void)
+{
+ frchainS *frchP;
+
+ /* When this routine is called, all of the subsections are still intact
+ so we walk over subsections instead of sections. */
+ for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
+ {
+ fragS *fragP;
+
+ /* Walk over all of the fragments in a subsection. */
+ for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+ {
+ if (fragP->fr_type == rs_machine_dependent
+ && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
+ {
+ if (next_frag_is_branch_target (fragP))
+ fragP->fr_subtype = RELAX_DESIRE_ALIGN;
+ else
+ frag_wane (fragP);
+ }
+ }
+ }