-@item .line
-@cindex @code{line} directive, AMD 29K
-This directive is ignored; it is accepted for compatibility with other
-AMD 29K assemblers.
-
-@ignore
-@c since we're ignoring .lsym...
-@item .reg @var{symbol}, @var{expression}
-@cindex @code{reg} directive, AMD 29K
-@code{.reg} has the same effect as @code{.lsym}; @pxref{Lsym,,@code{.lsym}}.
-@end ignore
-
-@item .sect
-@cindex @code{sect} directive, AMD 29K
-This directive is ignored; it is accepted for compatibility with other
-AMD 29K assemblers.
-
-@item .use @var{section name}
-@cindex @code{use} directive, AMD 29K
-Establishes the section and subsection for the following code;
-@var{section name} may be one of @code{.text}, @code{.data},
-@code{.data1}, or @code{.lit}. With one of the first three @var{section
-name} options, @samp{.use} is equivalent to the machine directive
-@var{section name}; the remaining case, @samp{.use .lit}, is the same as
-@samp{.data 200}.
-@end table
-
-@node AMD29K Opcodes
-@section Opcodes
-
-@cindex AMD 29K opcodes
-@cindex opcodes for AMD 29K
-@code{@value{AS}} implements all the standard AMD 29K opcodes. No
-additional pseudo-instructions are needed on this family.
-
-For information on the 29K machine instruction set, see @cite{Am29000
-User's Manual}, Advanced Micro Devices, Inc.
-
-@end ifset
-@ifset Hitachi-all
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter Machine Dependent Features
-
-The machine instruction sets are different on each Hitachi chip family,
-and there are also some syntax differences among the families. This
-chapter describes the specific @code{@value{AS}} features for each
-family.
-
-@menu
-* H8/300-Dependent:: Hitachi H8/300 Dependent Features
-* H8/500-Dependent:: Hitachi H8/500 Dependent Features
-* SH-Dependent:: Hitachi SH Dependent Features
-@end menu
-@lowersections
-@end ifclear
-@end ifset
-
-@ifset H8/300
-@ifset GENERIC
-@page
-@end ifset
-@node H8/300-Dependent
-@chapter H8/300 Dependent Features
-
-@cindex H8/300 support
-@menu
-* H8/300 Options:: Options
-* H8/300 Syntax:: Syntax
-* H8/300 Floating Point:: Floating Point
-* H8/300 Directives:: H8/300 Machine Directives
-* H8/300 Opcodes:: Opcodes
-@end menu
-
-@node H8/300 Options
-@section Options
-
-@cindex H8/300 options (none)
-@cindex options, H8/300 (none)
-@code{@value{AS}} has no additional command-line options for the Hitachi
-H8/300 family.
-
-@node H8/300 Syntax
-@section Syntax
-@menu
-* H8/300-Chars:: Special Characters
-* H8/300-Regs:: Register Names
-* H8/300-Addressing:: Addressing Modes
-@end menu
-
-@node H8/300-Chars
-@subsection Special Characters
-
-@cindex line comment character, H8/300
-@cindex H8/300 line comment character
-@samp{;} is the line comment character.
-
-@cindex line separator, H8/300
-@cindex statement separator, H8/300
-@cindex H8/300 line separator
-@samp{$} can be used instead of a newline to separate statements.
-Therefore @emph{you may not use @samp{$} in symbol names} on the H8/300.
-
-@node H8/300-Regs
-@subsection Register Names
-
-@cindex H8/300 registers
-@cindex register names, H8/300
-You can use predefined symbols of the form @samp{r@var{n}h} and
-@samp{r@var{n}l} to refer to the H8/300 registers as sixteen 8-bit
-general-purpose registers. @var{n} is a digit from @samp{0} to
-@samp{7}); for instance, both @samp{r0h} and @samp{r7l} are valid
-register names.
-
-You can also use the eight predefined symbols @samp{r@var{n}} to refer
-to the H8/300 registers as 16-bit registers (you must use this form for
-addressing).
-
-On the H8/300H, you can also use the eight predefined symbols
-@samp{er@var{n}} (@samp{er0} @dots{} @samp{er7}) to refer to the 32-bit
-general purpose registers.
-
-The two control registers are called @code{pc} (program counter; a
-16-bit register, except on the H8/300H where it is 24 bits) and
-@code{ccr} (condition code register; an 8-bit register). @code{r7} is
-used as the stack pointer, and can also be called @code{sp}.
-
-@node H8/300-Addressing
-@subsection Addressing Modes
-
-@cindex addressing modes, H8/300
-@cindex H8/300 addressing modes
-@value{AS} understands the following addressing modes for the H8/300:
-@table @code
-@item r@var{n}
-Register direct
-
-@item @@r@var{n}
-Register indirect
-
-@item @@(@var{d}, r@var{n})
-@itemx @@(@var{d}:16, r@var{n})
-@itemx @@(@var{d}:24, r@var{n})
-Register indirect: 16-bit or 24-bit displacement @var{d} from register
-@var{n}. (24-bit displacements are only meaningful on the H8/300H.)
-
-@item @@r@var{n}+
-Register indirect with post-increment
-
-@item @@-r@var{n}
-Register indirect with pre-decrement
-
-@item @code{@@}@var{aa}
-@itemx @code{@@}@var{aa}:8
-@itemx @code{@@}@var{aa}:16
-@itemx @code{@@}@var{aa}:24
-Absolute address @code{aa}. (The address size @samp{:24} only makes
-sense on the H8/300H.)
-
-@item #@var{xx}
-@itemx #@var{xx}:8
-@itemx #@var{xx}:16
-@itemx #@var{xx}:32
-Immediate data @var{xx}. You may specify the @samp{:8}, @samp{:16}, or
-@samp{:32} for clarity, if you wish; but @code{@value{AS}} neither
-requires this nor uses it---the data size required is taken from
-context.
-
-@item @code{@@}@code{@@}@var{aa}
-@itemx @code{@@}@code{@@}@var{aa}:8
-Memory indirect. You may specify the @samp{:8} for clarity, if you
-wish; but @code{@value{AS}} neither requires this nor uses it.
-@end table
-
-@node H8/300 Floating Point
-@section Floating Point
-
-@cindex floating point, H8/300 (@sc{ieee})
-@cindex H8/300 floating point (@sc{ieee})
-The H8/300 family has no hardware floating point, but the @code{.float}
-directive generates @sc{ieee} floating-point numbers for compatibility
-with other development tools.
-
-@page
-@node H8/300 Directives
-@section H8/300 Machine Directives
-
-@cindex H8/300 machine directives (none)
-@cindex machine directives, H8/300 (none)
-@cindex @code{word} directive, H8/300
-@cindex @code{int} directive, H8/300
-@code{@value{AS}} has only one machine-dependent directive for the
-H8/300:
-
-@table @code
-@item .h300h
-@cindex H8/300H, assembling for
-Recognize and emit additional instructions for the H8/300H variant, and
-also make @code{.int} emit 32-bit numbers rather than the usual (16-bit)
-for the H8/300 family.
-@end table
-
-On the H8/300 family (including the H8/300H) @samp{.word} directives
-generate 16-bit numbers.
-
-@node H8/300 Opcodes
-@section Opcodes
-
-@cindex H8/300 opcode summary
-@cindex opcode summary, H8/300
-@cindex mnemonics, H8/300
-@cindex instruction summary, H8/300
-For detailed information on the H8/300 machine instruction set, see
-@cite{H8/300 Series Programming Manual} (Hitachi ADE--602--025). For
-information specific to the H8/300H, see @cite{H8/300H Series
-Programming Manual} (Hitachi).
-
-@code{@value{AS}} implements all the standard H8/300 opcodes. No additional
-pseudo-instructions are needed on this family.
-
-The following table summarizes the H8/300 opcodes, and their arguments.
-Entries marked @samp{*} are opcodes used only on the H8/300H.
-
-@smallexample
-@c Using @group seems to use the normal baselineskip, not the smallexample
-@c baselineskip; looks approx doublespaced.
- @i{Legend:}
- Rs @r{source register}
- Rd @r{destination register}
- abs @r{absolute address}
- imm @r{immediate data}
- disp:N @r{N-bit displacement from a register}
- pcrel:N @r{N-bit displacement relative to program counter}
-
- add.b #imm,rd * andc #imm,ccr
- add.b rs,rd band #imm,rd
- add.w rs,rd band #imm,@@rd
-* add.w #imm,rd band #imm,@@abs:8
-* add.l rs,rd bra pcrel:8
-* add.l #imm,rd * bra pcrel:16
- adds #imm,rd bt pcrel:8
- addx #imm,rd * bt pcrel:16
- addx rs,rd brn pcrel:8
- and.b #imm,rd * brn pcrel:16
- and.b rs,rd bf pcrel:8
-* and.w rs,rd * bf pcrel:16
-* and.w #imm,rd bhi pcrel:8
-* and.l #imm,rd * bhi pcrel:16
-* and.l rs,rd bls pcrel:8
-@page
-* bls pcrel:16 bld #imm,rd
- bcc pcrel:8 bld #imm,@@rd
-* bcc pcrel:16 bld #imm,@@abs:8
- bhs pcrel:8 bnot #imm,rd
-* bhs pcrel:16 bnot #imm,@@rd
- bcs pcrel:8 bnot #imm,@@abs:8
-* bcs pcrel:16 bnot rs,rd
- blo pcrel:8 bnot rs,@@rd
-* blo pcrel:16 bnot rs,@@abs:8
- bne pcrel:8 bor #imm,rd
-* bne pcrel:16 bor #imm,@@rd
- beq pcrel:8 bor #imm,@@abs:8
-* beq pcrel:16 bset #imm,rd
- bvc pcrel:8 bset #imm,@@rd
-* bvc pcrel:16 bset #imm,@@abs:8
- bvs pcrel:8 bset rs,rd
-* bvs pcrel:16 bset rs,@@rd
- bpl pcrel:8 bset rs,@@abs:8
-* bpl pcrel:16 bsr pcrel:8
- bmi pcrel:8 bsr pcrel:16
-* bmi pcrel:16 bst #imm,rd
- bge pcrel:8 bst #imm,@@rd
-* bge pcrel:16 bst #imm,@@abs:8
- blt pcrel:8 btst #imm,rd
-* blt pcrel:16 btst #imm,@@rd
- bgt pcrel:8 btst #imm,@@abs:8
-* bgt pcrel:16 btst rs,rd
- ble pcrel:8 btst rs,@@rd
-* ble pcrel:16 btst rs,@@abs:8
- bclr #imm,rd bxor #imm,rd
- bclr #imm,@@rd bxor #imm,@@rd
- bclr #imm,@@abs:8 bxor #imm,@@abs:8
- bclr rs,rd cmp.b #imm,rd
- bclr rs,@@rd cmp.b rs,rd
- bclr rs,@@abs:8 cmp.w rs,rd
- biand #imm,rd cmp.w rs,rd
- biand #imm,@@rd * cmp.w #imm,rd
- biand #imm,@@abs:8 * cmp.l #imm,rd
- bild #imm,rd * cmp.l rs,rd
- bild #imm,@@rd daa rs
- bild #imm,@@abs:8 das rs
- bior #imm,rd dec.b rs
- bior #imm,@@rd * dec.w #imm,rd
- bior #imm,@@abs:8 * dec.l #imm,rd
- bist #imm,rd divxu.b rs,rd
- bist #imm,@@rd * divxu.w rs,rd
- bist #imm,@@abs:8 * divxs.b rs,rd
- bixor #imm,rd * divxs.w rs,rd
- bixor #imm,@@rd eepmov
- bixor #imm,@@abs:8 * eepmovw
-@page
-* exts.w rd mov.w rs,@@abs:16
-* exts.l rd * mov.l #imm,rd
-* extu.w rd * mov.l rs,rd
-* extu.l rd * mov.l @@rs,rd
- inc rs * mov.l @@(disp:16,rs),rd
-* inc.w #imm,rd * mov.l @@(disp:24,rs),rd
-* inc.l #imm,rd * mov.l @@rs+,rd
- jmp @@rs * mov.l @@abs:16,rd
- jmp abs * mov.l @@abs:24,rd
- jmp @@@@abs:8 * mov.l rs,@@rd
- jsr @@rs * mov.l rs,@@(disp:16,rd)
- jsr abs * mov.l rs,@@(disp:24,rd)
- jsr @@@@abs:8 * mov.l rs,@@-rd
- ldc #imm,ccr * mov.l rs,@@abs:16
- ldc rs,ccr * mov.l rs,@@abs:24
-* ldc @@abs:16,ccr movfpe @@abs:16,rd
-* ldc @@abs:24,ccr movtpe rs,@@abs:16
-* ldc @@(disp:16,rs),ccr mulxu.b rs,rd
-* ldc @@(disp:24,rs),ccr * mulxu.w rs,rd
-* ldc @@rs+,ccr * mulxs.b rs,rd
-* ldc @@rs,ccr * mulxs.w rs,rd
-* mov.b @@(disp:24,rs),rd neg.b rs
-* mov.b rs,@@(disp:24,rd) * neg.w rs
- mov.b @@abs:16,rd * neg.l rs
- mov.b rs,rd nop
- mov.b @@abs:8,rd not.b rs
- mov.b rs,@@abs:8 * not.w rs
- mov.b rs,rd * not.l rs
- mov.b #imm,rd or.b #imm,rd
- mov.b @@rs,rd or.b rs,rd
- mov.b @@(disp:16,rs),rd * or.w #imm,rd
- mov.b @@rs+,rd * or.w rs,rd
- mov.b @@abs:8,rd * or.l #imm,rd
- mov.b rs,@@rd * or.l rs,rd
- mov.b rs,@@(disp:16,rd) orc #imm,ccr
- mov.b rs,@@-rd pop.w rs
- mov.b rs,@@abs:8 * pop.l rs
- mov.w rs,@@rd push.w rs
-* mov.w @@(disp:24,rs),rd * push.l rs
-* mov.w rs,@@(disp:24,rd) rotl.b rs
-* mov.w @@abs:24,rd * rotl.w rs
-* mov.w rs,@@abs:24 * rotl.l rs
- mov.w rs,rd rotr.b rs
- mov.w #imm,rd * rotr.w rs
- mov.w @@rs,rd * rotr.l rs
- mov.w @@(disp:16,rs),rd rotxl.b rs
- mov.w @@rs+,rd * rotxl.w rs
- mov.w @@abs:16,rd * rotxl.l rs
- mov.w rs,@@(disp:16,rd) rotxr.b rs
- mov.w rs,@@-rd * rotxr.w rs
-@page
-* rotxr.l rs * stc ccr,@@(disp:24,rd)
- bpt * stc ccr,@@-rd
- rte * stc ccr,@@abs:16
- rts * stc ccr,@@abs:24
- shal.b rs sub.b rs,rd
-* shal.w rs sub.w rs,rd
-* shal.l rs * sub.w #imm,rd
- shar.b rs * sub.l rs,rd
-* shar.w rs * sub.l #imm,rd
-* shar.l rs subs #imm,rd
- shll.b rs subx #imm,rd
-* shll.w rs subx rs,rd
-* shll.l rs * trapa #imm
- shlr.b rs xor #imm,rd
-* shlr.w rs xor rs,rd
-* shlr.l rs * xor.w #imm,rd
- sleep * xor.w rs,rd
- stc ccr,rd * xor.l #imm,rd
-* stc ccr,@@rs * xor.l rs,rd
-* stc ccr,@@(disp:16,rd) xorc #imm,ccr
-@end smallexample
-
-@cindex size suffixes, H8/300
-@cindex H8/300 size suffixes
-Four H8/300 instructions (@code{add}, @code{cmp}, @code{mov},
-@code{sub}) are defined with variants using the suffixes @samp{.b},
-@samp{.w}, and @samp{.l} to specify the size of a memory operand.
-@code{@value{AS}} supports these suffixes, but does not require them;
-since one of the operands is always a register, @code{@value{AS}} can
-deduce the correct size.
-
-For example, since @code{r0} refers to a 16-bit register,
-@example
-mov r0,@@foo
-@exdent is equivalent to
-mov.w r0,@@foo
-@end example
-
-If you use the size suffixes, @code{@value{AS}} issues a warning when
-the suffix and the register size do not match.
-@end ifset
-
-@ifset H8/500
-@page
-@node H8/500-Dependent
-@chapter H8/500 Dependent Features
-
-@cindex H8/500 support
-@menu
-* H8/500 Options:: Options
-* H8/500 Syntax:: Syntax
-* H8/500 Floating Point:: Floating Point
-* H8/500 Directives:: H8/500 Machine Directives
-* H8/500 Opcodes:: Opcodes
-@end menu
-
-@node H8/500 Options
-@section Options
-
-@cindex H8/500 options (none)
-@cindex options, H8/500 (none)
-@code{@value{AS}} has no additional command-line options for the Hitachi
-H8/500 family.
-
-@node H8/500 Syntax
-@section Syntax
-
-@menu
-* H8/500-Chars:: Special Characters
-* H8/500-Regs:: Register Names
-* H8/500-Addressing:: Addressing Modes
-@end menu
-
-@node H8/500-Chars
-@subsection Special Characters
-
-@cindex line comment character, H8/500
-@cindex H8/500 line comment character
-@samp{!} is the line comment character.
-
-@cindex line separator, H8/500
-@cindex statement separator, H8/500
-@cindex H8/500 line separator
-@samp{;} can be used instead of a newline to separate statements.
-
-@cindex symbol names, @samp{$} in
-@cindex @code{$} in symbol names
-Since @samp{$} has no special meaning, you may use it in symbol names.
-
-@node H8/500-Regs
-@subsection Register Names
-
-@cindex H8/500 registers
-@cindex registers, H8/500
-You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
-@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, and @samp{r7} to refer to
-the H8/500 registers.
-
-The H8/500 also has these control registers:
-
-@table @code
-@item cp
-code pointer
-
-@item dp
-data pointer
-
-@item bp
-base pointer
-
-@item tp
-stack top pointer
-
-@item ep
-extra pointer
-
-@item sr
-status register
-
-@item ccr
-condition code register
-@end table
-
-All registers are 16 bits long. To represent 32 bit numbers, use two
-adjacent registers; for distant memory addresses, use one of the segment
-pointers (@code{cp} for the program counter; @code{dp} for
-@code{r0}--@code{r3}; @code{ep} for @code{r4} and @code{r5}; and
-@code{tp} for @code{r6} and @code{r7}.
-
-@node H8/500-Addressing
-@subsection Addressing Modes
-
-@cindex addressing modes, H8/500
-@cindex H8/500 addressing modes
-@value{AS} understands the following addressing modes for the H8/500:
-@table @code
-@item R@var{n}
-Register direct
-
-@item @@R@var{n}
-Register indirect
-
-@item @@(d:8, R@var{n})
-Register indirect with 8 bit signed displacement
-
-@item @@(d:16, R@var{n})
-Register indirect with 16 bit signed displacement
-
-@item @@-R@var{n}
-Register indirect with pre-decrement
-
-@item @@R@var{n}+
-Register indirect with post-increment
-
-@item @@@var{aa}:8
-8 bit absolute address
-
-@item @@@var{aa}:16
-16 bit absolute address
-
-@item #@var{xx}:8
-8 bit immediate
-
-@item #@var{xx}:16
-16 bit immediate
-@end table
-
-@node H8/500 Floating Point
-@section Floating Point
-
-@cindex floating point, H8/500 (@sc{ieee})
-@cindex H8/500 floating point (@sc{ieee})
-The H8/500 family uses @sc{ieee} floating-point numbers.
-
-@node H8/500 Directives
-@section H8/500 Machine Directives
-
-@cindex H8/500 machine directives (none)
-@cindex machine directives, H8/500 (none)
-@cindex @code{word} directive, H8/500
-@cindex @code{int} directive, H8/500
-@code{@value{AS}} has no machine-dependent directives for the H8/500.
-However, on this platform the @samp{.int} and @samp{.word} directives
-generate 16-bit numbers.
-
-@node H8/500 Opcodes
-@section Opcodes
-
-@cindex H8/500 opcode summary
-@cindex opcode summary, H8/500
-@cindex mnemonics, H8/500
-@cindex instruction summary, H8/500
-For detailed information on the H8/500 machine instruction set, see
-@cite{H8/500 Series Programming Manual} (Hitachi M21T001).
-
-@code{@value{AS}} implements all the standard H8/500 opcodes. No additional
-pseudo-instructions are needed on this family.
-
-The following table summarizes H8/500 opcodes and their operands:
-
-@c Use @group if it ever works, instead of @page
-@page
-@smallexample
-@i{Legend:}
-abs8 @r{8-bit absolute address}
-abs16 @r{16-bit absolute address}
-abs24 @r{24-bit absolute address}
-crb @r{@code{ccr}, @code{br}, @code{ep}, @code{dp}, @code{tp}, @code{dp}}
-disp8 @r{8-bit displacement}
-ea @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
- @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16},}
- @r{@code{#xx:8}, @code{#xx:16}}
-ea_mem @r{@code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
- @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}}
-ea_noimm @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
- @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}}
-fp r6
-imm4 @r{4-bit immediate data}
-imm8 @r{8-bit immediate data}
-imm16 @r{16-bit immediate data}
-pcrel8 @r{8-bit offset from program counter}
-pcrel16 @r{16-bit offset from program counter}
-qim @r{@code{-2}, @code{-1}, @code{1}, @code{2}}
-rd @r{any register}
-rs @r{a register distinct from rd}
-rlist @r{comma-separated list of registers in parentheses;}
- @r{register ranges @code{rd-rs} are allowed}
-sp @r{stack pointer (@code{r7})}
-sr @r{status register}
-sz @r{size; @samp{.b} or @samp{.w}. If omitted, default @samp{.w}}
-
-ldc[.b] ea,crb bcc[.w] pcrel16
-ldc[.w] ea,sr bcc[.b] pcrel8
-add[:q] sz qim,ea_noimm bhs[.w] pcrel16
-add[:g] sz ea,rd bhs[.b] pcrel8
-adds sz ea,rd bcs[.w] pcrel16
-addx sz ea,rd bcs[.b] pcrel8
-and sz ea,rd blo[.w] pcrel16
-andc[.b] imm8,crb blo[.b] pcrel8
-andc[.w] imm16,sr bne[.w] pcrel16
-bpt bne[.b] pcrel8
-bra[.w] pcrel16 beq[.w] pcrel16
-bra[.b] pcrel8 beq[.b] pcrel8
-bt[.w] pcrel16 bvc[.w] pcrel16
-bt[.b] pcrel8 bvc[.b] pcrel8
-brn[.w] pcrel16 bvs[.w] pcrel16
-brn[.b] pcrel8 bvs[.b] pcrel8
-bf[.w] pcrel16 bpl[.w] pcrel16
-bf[.b] pcrel8 bpl[.b] pcrel8
-bhi[.w] pcrel16 bmi[.w] pcrel16
-bhi[.b] pcrel8 bmi[.b] pcrel8
-bls[.w] pcrel16 bge[.w] pcrel16
-bls[.b] pcrel8 bge[.b] pcrel8
-@page
-blt[.w] pcrel16 mov[:g][.b] imm8,ea_mem
-blt[.b] pcrel8 mov[:g][.w] imm16,ea_mem
-bgt[.w] pcrel16 movfpe[.b] ea,rd
-bgt[.b] pcrel8 movtpe[.b] rs,ea_noimm
-ble[.w] pcrel16 mulxu sz ea,rd
-ble[.b] pcrel8 neg sz ea
-bclr sz imm4,ea_noimm nop
-bclr sz rs,ea_noimm not sz ea
-bnot sz imm4,ea_noimm or sz ea,rd
-bnot sz rs,ea_noimm orc[.b] imm8,crb
-bset sz imm4,ea_noimm orc[.w] imm16,sr
-bset sz rs,ea_noimm pjmp abs24
-bsr[.b] pcrel8 pjmp @@rd
-bsr[.w] pcrel16 pjsr abs24
-btst sz imm4,ea_noimm pjsr @@rd
-btst sz rs,ea_noimm prtd imm8
-clr sz ea prtd imm16
-cmp[:e][.b] imm8,rd prts
-cmp[:i][.w] imm16,rd rotl sz ea
-cmp[:g].b imm8,ea_noimm rotr sz ea
-cmp[:g][.w] imm16,ea_noimm rotxl sz ea
-Cmp[:g] sz ea,rd rotxr sz ea
-dadd rs,rd rtd imm8
-divxu sz ea,rd rtd imm16
-dsub rs,rd rts
-exts[.b] rd scb/f rs,pcrel8
-extu[.b] rd scb/ne rs,pcrel8
-jmp @@rd scb/eq rs,pcrel8
-jmp @@(imm8,rd) shal sz ea
-jmp @@(imm16,rd) shar sz ea
-jmp abs16 shll sz ea
-jsr @@rd shlr sz ea
-jsr @@(imm8,rd) sleep
-jsr @@(imm16,rd) stc[.b] crb,ea_noimm
-jsr abs16 stc[.w] sr,ea_noimm
-ldm @@sp+,(rlist) stm (rlist),@@-sp
-link fp,imm8 sub sz ea,rd
-link fp,imm16 subs sz ea,rd
-mov[:e][.b] imm8,rd subx sz ea,rd
-mov[:i][.w] imm16,rd swap[.b] rd
-mov[:l][.w] abs8,rd tas[.b] ea
-mov[:l].b abs8,rd trapa imm4
-mov[:s][.w] rs,abs8 trap/vs
-mov[:s].b rs,abs8 tst sz ea
-mov[:f][.w] @@(disp8,fp),rd unlk fp
-mov[:f][.w] rs,@@(disp8,fp) xch[.w] rs,rd
-mov[:f].b @@(disp8,fp),rd xor sz ea,rd
-mov[:f].b rs,@@(disp8,fp) xorc.b imm8,crb
-mov[:g] sz rs,ea_mem xorc.w imm16,sr
-mov[:g] sz ea,rd
-@end smallexample
-
-@end ifset
-
-@ifset HPPA
-@page
-@node HPPA-Dependent
-@chapter HPPA Dependent Features
-
-@cindex support
-@menu
-* HPPA Notes:: Notes
-* HPPA Options:: Options
-* HPPA Syntax:: Syntax
-* HPPA Floating Point:: Floating Point
-* HPPA Directives:: HPPA Machine Directives
-* HPPA Opcodes:: Opcodes
-@end menu
-
-@node HPPA Notes
-@section Notes
-As a back end for GNU CC @code{@value{AS}} has been throughly tested and should
-work extremely well. We have tested it only minimally on hand written assembly
-code and no one has tested it much on the assembly output from the HP
-compilers.
-
-The format of the debugging sections has changed since the original
-@code{@value{AS}} port (version 1.3X) was released; therefore,
-you must rebuild all objects and libraries with the new
-assembler so that you can debug the final executable.
-
-The HPPA @code{@value{AS}} port generates a small subset of the relocations
-available in the SOM and ELF object file formats. Additional relocation
-support will be added as it becomes necessary.
-
-@node HPPA Options
-@section Options
-@code{@value{AS}} has no machine-dependent directives for the HPPA.
-
-@cindex HPPA Syntax
-@node HPPA Syntax
-@section Syntax
-The assembler syntax closely follows the HPPA instruction set
-reference manual; assembler directives and general syntax closely follow the
-HPPA assembly language reference manual with a few noteworthy differences.
-
-First a colon may immediately follow a label definition. This is
-simply for compatability with how most assembly language programmers
-write code.
-
-Some obscure expression parsing problems may affect hand written code which
-uses the @code{spop} instructions, or code which makes significant
-use of the @code{!} line separator.
-
-@code{@value{AS}} is much less forgiving about missing arguments and other
-similar oversights. @code{@value{AS}} will flag missing arguments as
-syntax errors; this is regarded as a feature, not a bug.
-
-Finally, @code{@value{AS}} allows you to use an external symbol without
-explicitly importing the symbol. @emph{Warning:} in the future this will be
-an error for HPPA targets.
-
-Special characters for HPPA targets include:
-
-@samp{;} is the line comment character.
-
-@samp{!} can be used instead of a newline to separate statements.
-
-Since @samp{$} has no special meaning, you may use it in symbol names.
-
-@node HPPA Floating Point
-@section Floating Point
-@cindex floating point, HPPA (@sc{ieee})
-@cindex HPPA floating point (@sc{ieee})
-The HPPA family uses @sc{ieee} floating-point numbers.
-
-@node HPPA Directives
-@section HPPA Machine Directives
-For detailed information on the HPPA machine instruction set, see
-@cite{HP9000 Series 800 Assembly Language Reference Manual}
-(HP 92432-90001).
-
-@code{@value{AS}} does not support the following assembler directives
-found in the HP manual:
-@itemize @bullet
-@item endm
-@item enter
-@item leave
-@item listoff
-@item liston
-@item locct
-@item macro
-@end itemize
-
-@code{@value{AS}} supports one additional assembler directive for the
-HPPA: @code{.PARAM}. It conveys register argument locations for
-static functions. Its syntax closely follows the @code{.EXPORT} directive.
-
-@node HPPA Opcodes
-@section Opcodes
-For detailed information on the HPPA machine instruction set, see
-@cite{PA-RISC Architecture and Instruction Set Reference Manual}
-(HP 09740-90039).
-@end ifset
-
-@ifset SH
-@page
-@node SH-Dependent
-@chapter Hitachi SH Dependent Features
-
-@cindex SH support
-@menu
-* SH Options:: Options
-* SH Syntax:: Syntax
-* SH Floating Point:: Floating Point
-* SH Directives:: SH Machine Directives
-* SH Opcodes:: Opcodes
-@end menu
-
-@node SH Options
-@section Options
-
-@cindex SH options (none)
-@cindex options, SH (none)
-@code{@value{AS}} has no additional command-line options for the Hitachi
-SH family.
-
-@node SH Syntax
-@section Syntax
-
-@menu
-* SH-Chars:: Special Characters
-* SH-Regs:: Register Names
-* SH-Addressing:: Addressing Modes
-@end menu
-
-@node SH-Chars
-@subsection Special Characters
-
-@cindex line comment character, SH
-@cindex SH line comment character
-@samp{!} is the line comment character.
-
-@cindex line separator, SH
-@cindex statement separator, SH
-@cindex SH line separator
-You can use @samp{;} instead of a newline to separate statements.
-
-@cindex symbol names, @samp{$} in
-@cindex @code{$} in symbol names
-Since @samp{$} has no special meaning, you may use it in symbol names.
-
-@node SH-Regs
-@subsection Register Names
-
-@cindex SH registers
-@cindex registers, SH
-You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
-@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
-@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
-and @samp{r15} to refer to the SH registers.
-
-The SH also has these control registers:
-
-@table @code
-@item pr
-procedure register (holds return address)
-
-@item pc
-program counter
-
-@item mach
-@itemx macl
-high and low multiply accumulator registers
-
-@item sr
-status register
-
-@item gbr
-global base register
-
-@item vbr
-vector base register (for interrupt vectors)
-@end table
-
-@node SH-Addressing
-@subsection Addressing Modes
-
-@cindex addressing modes, SH
-@cindex SH addressing modes
-@code{@value{AS}} understands the following addressing modes for the SH.
-@code{R@var{n}} in the following refers to any of the numbered
-registers, but @emph{not} the control registers.
-
-@table @code
-@item R@var{n}
-Register direct
-
-@item @@R@var{n}
-Register indirect
-
-@item @@-R@var{n}
-Register indirect with pre-decrement
-
-@item @@R@var{n}+
-Register indirect with post-increment
-
-@item @@(@var{disp}, R@var{n})
-Register indirect with displacement
-
-@item @@(R0, R@var{n})
-Register indexed
-
-@item @@(@var{disp}, GBR)
-@code{GBR} offset
-
-@item @@(R0, GBR)
-GBR indexed
-
-@item @var{addr}
-@itemx @@(@var{disp}, PC)
-PC relative address (for branch or for addressing memory). The
-@code{@value{AS}} implementation allows you to use the simpler form
-@var{addr} anywhere a PC relative address is called for; the alternate
-form is supported for compatibility with other assemblers.
-
-@item #@var{imm}
-Immediate data
-@end table
-
-@node SH Floating Point
-@section Floating Point
-
-@cindex floating point, SH (@sc{ieee})
-@cindex SH floating point (@sc{ieee})
-The SH family uses @sc{ieee} floating-point numbers.
-
-@node SH Directives
-@section SH Machine Directives
-
-@cindex SH machine directives (none)
-@cindex machine directives, SH (none)
-@cindex @code{word} directive, SH
-@cindex @code{int} directive, SH
-@code{@value{AS}} has no machine-dependent directives for the SH.
-
-@node SH Opcodes
-@section Opcodes
-
-@cindex SH opcode summary
-@cindex opcode summary, SH
-@cindex mnemonics, SH
-@cindex instruction summary, SH
-For detailed information on the SH machine instruction set, see
-@cite{SH-Microcomputer User's Manual} (Hitachi Micro Systems, Inc.).
-
-@code{@value{AS}} implements all the standard SH opcodes. No additional
-pseudo-instructions are needed on this family. Note, however, that
-because @code{@value{AS}} supports a simpler form of PC-relative
-addressing, you may simply write (for example)
-
-@example
-mov.l bar,r0
-@end example
-
-@noindent
-where other assemblers might require an explicit displacement to
-@code{bar} from the program counter:
-
-@example
-mov.l @@(@var{disp}, PC)
-@end example
-
-Here is a summary of SH opcodes:
-
-@page
-@smallexample
-@i{Legend:}
-Rn @r{a numbered register}
-Rm @r{another numbered register}
-#imm @r{immediate data}
-disp @r{displacement}
-disp8 @r{8-bit displacement}
-disp12 @r{12-bit displacement}
-
-add #imm,Rn lds.l @@Rn+,PR
-add Rm,Rn mac.w @@Rm+,@@Rn+
-addc Rm,Rn mov #imm,Rn
-addv Rm,Rn mov Rm,Rn
-and #imm,R0 mov.b Rm,@@(R0,Rn)
-and Rm,Rn mov.b Rm,@@-Rn
-and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
-bf disp8 mov.b @@(disp,Rm),R0
-bra disp12 mov.b @@(disp,GBR),R0
-bsr disp12 mov.b @@(R0,Rm),Rn
-bt disp8 mov.b @@Rm+,Rn
-clrm mov.b @@Rm,Rn
-clrt mov.b R0,@@(disp,Rm)
-cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
-cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
-cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
-cmp/gt Rm,Rn mov.l Rm,@@-Rn
-cmp/hi Rm,Rn mov.l Rm,@@Rn
-cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
-cmp/pl Rn mov.l @@(disp,GBR),R0
-cmp/pz Rn mov.l @@(disp,PC),Rn
-cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
-div0s Rm,Rn mov.l @@Rm+,Rn
-div0u mov.l @@Rm,Rn
-div1 Rm,Rn mov.l R0,@@(disp,GBR)
-exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
-exts.w Rm,Rn mov.w Rm,@@-Rn
-extu.b Rm,Rn mov.w Rm,@@Rn
-extu.w Rm,Rn mov.w @@(disp,Rm),R0
-jmp @@Rn mov.w @@(disp,GBR),R0
-jsr @@Rn mov.w @@(disp,PC),Rn
-ldc Rn,GBR mov.w @@(R0,Rm),Rn
-ldc Rn,SR mov.w @@Rm+,Rn
-ldc Rn,VBR mov.w @@Rm,Rn
-ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
-ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
-ldc.l @@Rn+,VBR mova @@(disp,PC),R0
-lds Rn,MACH movt Rn
-lds Rn,MACL muls Rm,Rn
-lds Rn,PR mulu Rm,Rn
-lds.l @@Rn+,MACH neg Rm,Rn
-lds.l @@Rn+,MACL negc Rm,Rn
-@page
-nop stc VBR,Rn
-not Rm,Rn stc.l GBR,@@-Rn
-or #imm,R0 stc.l SR,@@-Rn
-or Rm,Rn stc.l VBR,@@-Rn
-or.b #imm,@@(R0,GBR) sts MACH,Rn
-rotcl Rn sts MACL,Rn
-rotcr Rn sts PR,Rn
-rotl Rn sts.l MACH,@@-Rn
-rotr Rn sts.l MACL,@@-Rn
-rte sts.l PR,@@-Rn
-rts sub Rm,Rn
-sett subc Rm,Rn
-shal Rn subv Rm,Rn
-shar Rn swap.b Rm,Rn
-shll Rn swap.w Rm,Rn
-shll16 Rn tas.b @@Rn
-shll2 Rn trapa #imm
-shll8 Rn tst #imm,R0
-shlr Rn tst Rm,Rn
-shlr16 Rn tst.b #imm,@@(R0,GBR)
-shlr2 Rn xor #imm,R0
-shlr8 Rn xor Rm,Rn
-sleep xor.b #imm,@@(R0,GBR)
-stc GBR,Rn xtrct Rm,Rn
-stc SR,Rn
-@end smallexample
-
-@ifset Hitachi-all
-@ifclear GENERIC
-@raisesections
-@end ifclear
-@end ifset
-
-@end ifset
-@ifset I960
-@ifset GENERIC
-@page
-@node i960-Dependent
-@chapter Intel 80960 Dependent Features
-@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter Intel 80960 Dependent Features
-@end ifclear
-
-@cindex i960 support
-@menu
-* Options-i960:: i960 Command-line Options
-* Floating Point-i960:: Floating Point
-* Directives-i960:: i960 Machine Directives
-* Opcodes for i960:: i960 Opcodes
-@end menu
-
-@c FIXME! Add Syntax sec with discussion of bitfields here, at least so
-@c long as they're not turned on for other machines than 960.
-
-@node Options-i960
-
-@section i960 Command-line Options
-
-@cindex i960 options
-@cindex options, i960
-@table @code
-
-@item -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
-@cindex i960 architecture options
-@cindex architecture options, i960
-@cindex @code{-A} options, i960
-Select the 80960 architecture. Instructions or features not supported
-by the selected architecture cause fatal errors.
-
-@samp{-ACA} is equivalent to @samp{-ACA_A}; @samp{-AKC} is equivalent to
-@samp{-AMC}. Synonyms are provided for compatibility with other tools.
-
-If none of these options is specified, @code{@value{AS}} will generate code for any
-instruction or feature that is supported by @emph{some} version of the
-960 (even if this means mixing architectures!). In principle,
-@code{@value{AS}} will attempt to deduce the minimal sufficient processor
-type if none is specified; depending on the object code format, the
-processor type may be recorded in the object file. If it is critical
-that the @code{@value{AS}} output match a specific architecture, specify that
-architecture explicitly.
-
-@item -b
-@cindex @code{-b} option, i960
-@cindex branch recording, i960
-@cindex i960 branch recording
-Add code to collect information about conditional branches taken, for
-later optimization using branch prediction bits. (The conditional branch
-instructions have branch prediction bits in the CA, CB, and CC
-architectures.) If @var{BR} represents a conditional branch instruction,
-the following represents the code generated by the assembler when
-@samp{-b} is specified:
-
-@smallexample
- call @var{increment routine}
- .word 0 # pre-counter
-Label: @var{BR}
- call @var{increment routine}
- .word 0 # post-counter
-@end smallexample
-
-The counter following a branch records the number of times that branch
-was @emph{not} taken; the differenc between the two counters is the
-number of times the branch @emph{was} taken.
-
-@cindex @code{gbr960}, i960 postprocessor
-@cindex branch statistics table, i960
-A table of every such @code{Label} is also generated, so that the
-external postprocessor @code{gbr960} (supplied by Intel) can locate all
-the counters. This table is always labelled @samp{__BRANCH_TABLE__};
-this is a local symbol to permit collecting statistics for many separate
-object files. The table is word aligned, and begins with a two-word
-header. The first word, initialized to 0, is used in maintaining linked
-lists of branch tables. The second word is a count of the number of
-entries in the table, which follow immediately: each is a word, pointing
-to one of the labels illustrated above.
-
-@c TEXI2ROFF-KILL
-@ifinfo
-@c END TEXI2ROFF-KILL
-@example
- +------------+------------+------------+ ... +------------+
- | | | | | |
- | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N |
- | | | | | |
- +------------+------------+------------+ ... +------------+
-
- __BRANCH_TABLE__ layout
-@end example
-@c TEXI2ROFF-KILL
-@end ifinfo
-@tex
-\vskip 1pc
-\line{\leftskip=0pt\hskip\tableindent
-\boxit{2cm}{\tt *NEXT}\boxit{2cm}{\tt COUNT: \it N}\boxit{2cm}{\tt
-*BRLAB 1}\ibox{1cm}{\quad\dots}\boxit{2cm}{\tt *BRLAB \it N}\hfil}
-\centerline{\it {\tt \_\_BRANCH\_TABLE\_\_} layout}
-@end tex
-@c END TEXI2ROFF-KILL
-
-The first word of the header is used to locate multiple branch tables,
-since each object file may contain one. Normally the links are
-maintained with a call to an initialization routine, placed at the
-beginning of each function in the file. The GNU C compiler will
-generate these calls automatically when you give it a @samp{-b} option.
-For further details, see the documentation of @samp{gbr960}.
-
-@item -norelax
-@cindex @code{-norelax} option, i960
-Normally, Compare-and-Branch instructions with targets that require
-displacements greater than 13 bits (or that have external targets) are
-replaced with the corresponding compare (or @samp{chkbit}) and branch
-instructions. You can use the @samp{-norelax} option to specify that
-@code{@value{AS}} should generate errors instead, if the target displacement
-is larger than 13 bits.
-
-This option does not affect the Compare-and-Jump instructions; the code
-emitted for them is @emph{always} adjusted when necessary (depending on
-displacement size), regardless of whether you use @samp{-norelax}.
-@end table
-
-@node Floating Point-i960
-@section Floating Point
-
-@cindex floating point, i960 (@sc{ieee})
-@cindex i960 floating point (@sc{ieee})
-@code{@value{AS}} generates @sc{ieee} floating-point numbers for the directives
-@samp{.float}, @samp{.double}, @samp{.extended}, and @samp{.single}.
-
-@node Directives-i960
-@section i960 Machine Directives
-
-@cindex machine directives, i960
-@cindex i960 machine directives
-
-@table @code
-@cindex @code{bss} directive, i960
-@item .bss @var{symbol}, @var{length}, @var{align}
-Reserve @var{length} bytes in the bss section for a local @var{symbol},
-aligned to the power of two specified by @var{align}. @var{length} and
-@var{align} must be positive absolute expressions. This directive
-differs from @samp{.lcomm} only in that it permits you to specify
-an alignment. @xref{Lcomm,,@code{.lcomm}}.
-@end table
-
-@table @code
-@item .extended @var{flonums}
-@cindex @code{extended} directive, i960
-@code{.extended} expects zero or more flonums, separated by commas; for
-each flonum, @samp{.extended} emits an @sc{ieee} extended-format (80-bit)
-floating-point number.
-
-@item .leafproc @var{call-lab}, @var{bal-lab}
-@cindex @code{leafproc} directive, i960
-You can use the @samp{.leafproc} directive in conjunction with the
-optimized @code{callj} instruction to enable faster calls of leaf
-procedures. If a procedure is known to call no other procedures, you
-may define an entry point that skips procedure prolog code (and that does
-not depend on system-supplied saved context), and declare it as the
-@var{bal-lab} using @samp{.leafproc}. If the procedure also has an
-entry point that goes through the normal prolog, you can specify that
-entry point as @var{call-lab}.
-
-A @samp{.leafproc} declaration is meant for use in conjunction with the
-optimized call instruction @samp{callj}; the directive records the data
-needed later to choose between converting the @samp{callj} into a
-@code{bal} or a @code{call}.
-
-@var{call-lab} is optional; if only one argument is present, or if the
-two arguments are identical, the single argument is assumed to be the
-@code{bal} entry point.
-
-@item .sysproc @var{name}, @var{index}
-@cindex @code{sysproc} directive, i960
-The @samp{.sysproc} directive defines a name for a system procedure.
-After you define it using @samp{.sysproc}, you can use @var{name} to
-refer to the system procedure identified by @var{index} when calling
-procedures with the optimized call instruction @samp{callj}.
-
-Both arguments are required; @var{index} must be between 0 and 31
-(inclusive).
-@end table
-
-@node Opcodes for i960
-@section i960 Opcodes
-
-@cindex opcodes, i960
-@cindex i960 opcodes
-All Intel 960 machine instructions are supported;
-@pxref{Options-i960,,i960 Command-line Options} for a discussion of
-selecting the instruction subset for a particular 960
-architecture.@refill
-
-Some opcodes are processed beyond simply emitting a single corresponding
-instruction: @samp{callj}, and Compare-and-Branch or Compare-and-Jump
-instructions with target displacements larger than 13 bits.
-
-@menu
-* callj-i960:: @code{callj}
-* Compare-and-branch-i960:: Compare-and-Branch
-@end menu
-
-@node callj-i960
-@subsection @code{callj}
-
-@cindex @code{callj}, i960 pseudo-opcode
-@cindex i960 @code{callj} pseudo-opcode
-You can write @code{callj} to have the assembler or the linker determine
-the most appropriate form of subroutine call: @samp{call},
-@samp{bal}, or @samp{calls}. If the assembly source contains
-enough information---a @samp{.leafproc} or @samp{.sysproc} directive
-defining the operand---then @code{@value{AS}} will translate the
-@code{callj}; if not, it will simply emit the @code{callj}, leaving it
-for the linker to resolve.
-
-@node Compare-and-branch-i960
-@subsection Compare-and-Branch
-
-@cindex i960 compare/branch instructions
-@cindex compare/branch instructions, i960
-The 960 architectures provide combined Compare-and-Branch instructions
-that permit you to store the branch target in the lower 13 bits of the
-instruction word itself. However, if you specify a branch target far
-enough away that its address won't fit in 13 bits, the assembler can
-either issue an error, or convert your Compare-and-Branch instruction
-into separate instructions to do the compare and the branch.
-
-@cindex compare and jump expansions, i960
-@cindex i960 compare and jump expansions
-Whether @code{@value{AS}} gives an error or expands the instruction depends
-on two choices you can make: whether you use the @samp{-norelax} option,
-and whether you use a ``Compare and Branch'' instruction or a ``Compare
-and Jump'' instruction. The ``Jump'' instructions are @emph{always}
-expanded if necessary; the ``Branch'' instructions are expanded when
-necessary @emph{unless} you specify @code{-norelax}---in which case
-@code{@value{AS}} gives an error instead.
-
-These are the Compare-and-Branch instructions, their ``Jump'' variants,
-and the instruction pairs they may expand into:
-
-@c TEXI2ROFF-KILL
-@ifinfo
-@c END TEXI2ROFF-KILL
-@example
- Compare and
- Branch Jump Expanded to
- ------ ------ ------------
- bbc chkbit; bno
- bbs chkbit; bo
- cmpibe cmpije cmpi; be
- cmpibg cmpijg cmpi; bg
- cmpibge cmpijge cmpi; bge
- cmpibl cmpijl cmpi; bl
- cmpible cmpijle cmpi; ble
- cmpibno cmpijno cmpi; bno
- cmpibne cmpijne cmpi; bne
- cmpibo cmpijo cmpi; bo
- cmpobe cmpoje cmpo; be
- cmpobg cmpojg cmpo; bg
- cmpobge cmpojge cmpo; bge
- cmpobl cmpojl cmpo; bl
- cmpoble cmpojle cmpo; ble
- cmpobne cmpojne cmpo; bne
-@end example
-@c TEXI2ROFF-KILL
-@end ifinfo
-@tex
-\hskip\tableindent
-\halign{\hfil {\tt #}\quad&\hfil {\tt #}\qquad&{\tt #}\hfil\cr
-\omit{\hfil\it Compare and\hfil}\span\omit&\cr
-{\it Branch}&{\it Jump}&{\it Expanded to}\cr
- bbc& & chkbit; bno\cr
- bbs& & chkbit; bo\cr
- cmpibe& cmpije& cmpi; be\cr
- cmpibg& cmpijg& cmpi; bg\cr
- cmpibge& cmpijge& cmpi; bge\cr
- cmpibl& cmpijl& cmpi; bl\cr
- cmpible& cmpijle& cmpi; ble\cr
- cmpibno& cmpijno& cmpi; bno\cr
- cmpibne& cmpijne& cmpi; bne\cr
- cmpibo& cmpijo& cmpi; bo\cr
- cmpobe& cmpoje& cmpo; be\cr
- cmpobg& cmpojg& cmpo; bg\cr
- cmpobge& cmpojge& cmpo; bge\cr
- cmpobl& cmpojl& cmpo; bl\cr
- cmpoble& cmpojle& cmpo; ble\cr
- cmpobne& cmpojne& cmpo; bne\cr}
-@end tex
-@c END TEXI2ROFF-KILL
-@end ifset
-
-@ifset M680X0
-@ifset GENERIC
-@page
-@node M68K-Dependent
-@chapter M680x0 Dependent Features
-@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter M680x0 Dependent Features
-@end ifclear
-
-@cindex M680x0 support
-@menu
-* M68K-Opts:: M680x0 Options
-* M68K-Syntax:: Syntax
-* M68K-Moto-Syntax:: Motorola Syntax
-* M68K-Float:: Floating Point
-* M68K-Directives:: 680x0 Machine Directives
-* M68K-opcodes:: Opcodes
-@end menu
-
-@node M68K-Opts
-@section M680x0 Options
-
-@cindex options, M680x0
-@cindex M680x0 options
-The Motorola 680x0 version of @code{@value{AS}} has two machine dependent options.
-One shortens undefined references from 32 to 16 bits, while the
-other is used to tell @code{@value{AS}} what kind of machine it is
-assembling for.
-
-@cindex @code{-l} option, M680x0
-You can use the @kbd{-l} option to shorten the size of references to
-undefined symbols. If the @kbd{-l} option is not given, references to
-undefined symbols will be a full long (32 bits) wide. (Since @code{@value{AS}}
-cannot know where these symbols will end up, @code{@value{AS}} can only allocate
-space for the linker to fill in later. Since @code{@value{AS}} doesn't know how
-far away these symbols will be, it allocates as much space as it can.)
-If this option is given, the references will only be one word wide (16
-bits). This may be useful if you want the object file to be as small as
-possible, and you know that the relevant symbols will be less than 17
-bits away.
-
-@cindex @code{-m68000} and related options
-@cindex architecture options, M680x0
-@cindex M680x0 architecture options
-The 680x0 version of @code{@value{AS}} is most frequently used to assemble
-programs for the Motorola MC68020 microprocessor. Occasionally it is
-used to assemble programs for the mostly similar, but slightly different
-MC68000 or MC68010 microprocessors. You can give @code{@value{AS}} the options
-@samp{-m68000}, @samp{-mc68000}, @samp{-m68010}, @samp{-mc68010},
-@samp{-m68020}, and @samp{-mc68020} to tell it what processor is the
-target.
-
-@node M68K-Syntax
-@section Syntax
-
-@cindex @sc{mit}
-This syntax for the Motorola 680x0 was developed at @sc{mit}.
-
-@cindex M680x0 syntax
-@cindex syntax, M680x0
-@cindex M680x0 size modifiers
-@cindex size modifiers, M680x0
-The 680x0 version of @code{@value{AS}} uses syntax similar to the Sun
-assembler. Intervening periods are now ignored; for example, @samp{movl}
-is equivalent to @samp{move.l}.
-
-@ifset INTERNALS
-If @code{@value{AS}} is compiled with SUN_ASM_SYNTAX defined, it will
-also allow Sun-style local labels of the form @samp{1$} through
-@samp{$9}.
-@end ifset
-
-In the following table @dfn{apc} stands for any of the address
-registers (@samp{a0} through @samp{a7}), nothing, (@samp{}), the
-Program Counter (@samp{pc}), or the zero-address relative to the
-program counter (@samp{zpc}).
-
-@cindex M680x0 addressing modes
-@cindex addressing modes, M680x0
-The following addressing modes are understood:
-@table @dfn
-@item Immediate
-@samp{#@var{digits}}
-
-@item Data Register
-@samp{d0} through @samp{d7}
-
-@item Address Register
-@samp{a0} through @samp{a7}
-
-@item Address Register Indirect
-@samp{a0@@} through @samp{a7@@}@*
-@samp{a7} is also known as @samp{sp}, i.e. the Stack Pointer. @code{a6}
-is also known as @samp{fp}, the Frame Pointer.
-
-@item Address Register Postincrement
-@samp{a0@@+} through @samp{a7@@+}
-
-@item Address Register Predecrement
-@samp{a0@@-} through @samp{a7@@-}
-
-@item Indirect Plus Offset
-@samp{@var{apc}@@(@var{digits})}
-
-@item Index
-@samp{@var{apc}@@(@var{digits},@var{register}:@var{size}:@var{scale})}
-
-or @samp{@var{apc}@@(@var{register}:@var{size}:@var{scale})}
-
-@item Postindex
-@samp{@var{apc}@@(@var{digits})@@(@var{digits},@var{register}:@var{size}:@var{scale})}
-
-or @samp{@var{apc}@@(@var{digits})@@(@var{register}:@var{size}:@var{scale})}
-
-@item Preindex
-@samp{@var{apc}@@(@var{digits},@var{register}:@var{size}:@var{scale})@@(@var{digits})}
-
-or @samp{@var{apc}@@(@var{register}:@var{size}:@var{scale})@@(@var{digits})}
-
-@item Memory Indirect
-@samp{@var{apc}@@(@var{digits})@@(@var{digits})}
-
-@item Absolute
-@samp{@var{symbol}}, or @samp{@var{digits}}
-@ignore
-@c pesch@cygnus.com: gnu, rich concur the following needs careful
-@c research before documenting.
- , or either of the above followed
-by @samp{:b}, @samp{:w}, or @samp{:l}.
-@end ignore
-@end table
-
-For some configurations, especially those where the compiler normally
-does not prepend an underscore to the names of user variables, the
-assembler requires a @samp{%} before any use of a register name. This
-is intended to let the assembler distinguish between user variables and
-registers named @samp{a0} through @samp{a7}, et cetera. The @samp{%} is
-always accepted, but is only required for some configurations, notably
-@samp{m68k-coff}.
-
-@node M68K-Moto-Syntax
-@section Motorola Syntax
-
-@cindex Motorola syntax for the 680x0
-@cindex alternate syntax for the 680x0
-
-The standard Motorola syntax for this chip differs from the syntax
-already discussed (@pxref{M68K-Syntax,,Syntax}). @code{@value{AS}} can
-accept both kinds of syntax, even within a single instruction. The
-syntaxes are fully compatible, because the Motorola syntax never uses
-the @samp{@@} character and the @sc{mit} syntax always does, except in
-cases where the syntaxes are identical.
-
-@cindex M680x0 syntax
-@cindex syntax, M680x0
-In particular, you may write or generate M68K assembler with the
-following conventions:
-
-(In the following table @dfn{apc} stands for any of the address
-registers (@samp{a0} through @samp{a7}), nothing, (@samp{}), the
-Program Counter (@samp{pc}), or the zero-address relative to the
-program counter (@samp{zpc}).)
-
-@cindex M680x0 addressing modes
-@cindex addressing modes, M680x0
-The following additional addressing modes are understood:
-@table @dfn
-@item Address Register Indirect
-@samp{a0} through @samp{a7}@*
-@samp{a7} is also known as @samp{sp}, i.e. the Stack Pointer. @code{a6}
-is also known as @samp{fp}, the Frame Pointer.
-
-@item Address Register Postincrement
-@samp{(a0)+} through @samp{(a7)+}
-
-@item Address Register Predecrement
-@samp{-(a0)} through @samp{-(a7)}
-
-@item Indirect Plus Offset
-@samp{@var{digits}(@var{apc})}
-
-@item Index
-@samp{@var{digits}(@var{apc},(@var{register}.@var{size}*@var{scale})}@*
-or @samp{(@var{apc},@var{register}.@var{size}*@var{scale})}@*
-In either case, @var{size} and @var{scale} are optional
-(@var{scale} defaults to @samp{1}, @var{size} defaults to @samp{l}).
- @var{scale} can be @samp{1}, @samp{2}, @samp{4}, or @samp{8}.
- @var{size} can be @samp{w} or @samp{l}. @var{scale} is only supported
-on the 68020 and greater.
-@end table
-
-@node M68K-Float
-@section Floating Point
-
-@cindex floating point, M680x0
-@cindex M680x0 floating point
-@c FIXME is this "not too well tested" crud STILL true?
-The floating point code is not too well tested, and may have
-subtle bugs in it.
-
-Packed decimal (P) format floating literals are not supported.
-Feel free to add the code!
-
-The floating point formats generated by directives are these.
-
-@table @code
-@item .float
-@cindex @code{float} directive, M680x0
-@code{Single} precision floating point constants.
-
-@item .double
-@cindex @code{double} directive, M680x0
-@code{Double} precision floating point constants.
-@end table
-
-There is no directive to produce regions of memory holding
-extended precision numbers, however they can be used as
-immediate operands to floating-point instructions. Adding a
-directive to create extended precision numbers would not be
-hard, but it has not yet seemed necessary.
-
-@node M68K-Directives
-@section 680x0 Machine Directives
-
-@cindex M680x0 directives
-@cindex directives, M680x0
-In order to be compatible with the Sun assembler the 680x0 assembler
-understands the following directives.
-
-@table @code
-@item .data1
-@cindex @code{data1} directive, M680x0
-This directive is identical to a @code{.data 1} directive.
-
-@item .data2
-@cindex @code{data2} directive, M680x0
-This directive is identical to a @code{.data 2} directive.
-
-@item .even
-@cindex @code{even} directive, M680x0
-This directive is identical to a @code{.align 1} directive.
-@c Is this true? does it work???
-
-@item .skip
-@cindex @code{skip} directive, M680x0
-This directive is identical to a @code{.space} directive.
-@end table
-
-@node M68K-opcodes
-@section Opcodes
-
-@cindex M680x0 opcodes
-@cindex opcodes, M680x0
-@cindex instruction set, M680x0
-@c pesch@cygnus.com: I don't see any point in the following
-@c paragraph. Bugs are bugs; how does saying this
-@c help anyone?
-@ignore
-Danger: Several bugs have been found in the opcode table (and
-fixed). More bugs may exist. Be careful when using obscure
-instructions.
-@end ignore
-
-@menu
-* M68K-Branch:: Branch Improvement
-* M68K-Chars:: Special Characters
-@end menu
-
-@node M68K-Branch
-@subsection Branch Improvement
-
-@cindex pseudo-opcodes, M680x0
-@cindex M680x0 pseudo-opcodes
-@cindex branch improvement, M680x0
-@cindex M680x0 branch improvement
-Certain pseudo opcodes are permitted for branch instructions.
-They expand to the shortest branch instruction that will reach the
-target. Generally these mnemonics are made by substituting @samp{j} for
-@samp{b} at the start of a Motorola mnemonic.
-
-The following table summarizes the pseudo-operations. A @code{*} flags
-cases that are more fully described after the table:
-
-@smallexample
- Displacement
- +-------------------------------------------------
- | 68020 68000/10
-Pseudo-Op |BYTE WORD LONG LONG non-PC relative
- +-------------------------------------------------
- jbsr |bsrs bsr bsrl jsr jsr
- jra |bras bra bral jmp jmp
-* jXX |bXXs bXX bXXl bNXs;jmpl bNXs;jmp
-* dbXX |dbXX dbXX dbXX; bra; jmpl
-* fjXX |fbXXw fbXXw fbXXl fbNXw;jmp
-
-XX: condition
-NX: negative of condition XX
-
-@end smallexample
-@center @code{*}---see full description below
-
-@table @code
-@item jbsr
-@itemx jra
-These are the simplest jump pseudo-operations; they always map to one
-particular machine instruction, depending on the displacement to the
-branch target.
-
-@item j@var{XX}
-Here, @samp{j@var{XX}} stands for an entire family of pseudo-operations,
-where @var{XX} is a conditional branch or condition-code test. The full
-list of pseudo-ops in this family is:
-@smallexample
- jhi jls jcc jcs jne jeq jvc
- jvs jpl jmi jge jlt jgt jle
-@end smallexample
-
-For the cases of non-PC relative displacements and long displacements on
-the 68000 or 68010, @code{@value{AS}} will issue a longer code fragment in terms of
-@var{NX}, the opposite condition to @var{XX}. For example, for the
-non-PC relative case:
-@smallexample
- j@var{XX} foo
-@end smallexample
-gives
-@smallexample
- b@var{NX}s oof
- jmp foo
- oof:
-@end smallexample
-
-@item db@var{XX}
-The full family of pseudo-operations covered here is
-@smallexample
- dbhi dbls dbcc dbcs dbne dbeq dbvc
- dbvs dbpl dbmi dbge dblt dbgt dble
- dbf dbra dbt
-@end smallexample
-
-Other than for word and byte displacements, when the source reads
-@samp{db@var{XX} foo}, @code{@value{AS}} will emit
-@smallexample
- db@var{XX} oo1
- bra oo2
- oo1:jmpl foo
- oo2:
-@end smallexample
-
-@item fj@var{XX}
-This family includes
-@smallexample
- fjne fjeq fjge fjlt fjgt fjle fjf
- fjt fjgl fjgle fjnge fjngl fjngle fjngt
- fjnle fjnlt fjoge fjogl fjogt fjole fjolt
- fjor fjseq fjsf fjsne fjst fjueq fjuge
- fjugt fjule fjult fjun
-@end smallexample
-
-For branch targets that are not PC relative, @code{@value{AS}} emits
-@smallexample
- fb@var{NX} oof
- jmp foo
- oof:
-@end smallexample
-when it encounters @samp{fj@var{XX} foo}.
-
-@end table
-
-@node M68K-Chars
-@subsection Special Characters
-
-@cindex special characters, M680x0
-@cindex M680x0 immediate character
-@cindex immediate character, M680x0
-@cindex M680x0 line comment character
-@cindex line comment character, M680x0
-@cindex comments, M680x0
-The immediate character is @samp{#} for Sun compatibility. The
-line-comment character is @samp{|}. If a @samp{#} appears at the
-beginning of a line, it is treated as a comment unless it looks like
-@samp{# line file}, in which case it is treated normally.
-
-@end ifset
-@ignore
-@c FIXME! Stop ignoring when filled in.
-@node 32x32
-@chapter 32x32
-
-@section Options
-The 32x32 version of @code{@value{AS}} accepts a @kbd{-m32032} option to
-specify thiat it is compiling for a 32032 processor, or a
-@kbd{-m32532} to specify that it is compiling for a 32532 option.
-The default (if neither is specified) is chosen when the assembler
-is compiled.
-
-@section Syntax
-I don't know anything about the 32x32 syntax assembled by
-@code{@value{AS}}. Someone who undersands the processor (I've never seen
-one) and the possible syntaxes should write this section.
-
-@section Floating Point
-The 32x32 uses @sc{ieee} floating point numbers, but @code{@value{AS}}
-will only create single or double precision values. I don't know if the
-32x32 understands extended precision numbers.
-
-@section 32x32 Machine Directives
-The 32x32 has no machine dependent directives.
-
-@end ignore
-@ifset SPARC
-@ifset GENERIC
-@page
-@node Sparc-Dependent
-@chapter SPARC Dependent Features
-@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter SPARC Dependent Features
-@end ifclear
-
-@cindex SPARC support
-@menu
-* Sparc-Opts:: Options
-* Sparc-Float:: Floating Point
-* Sparc-Directives:: Sparc Machine Directives
-@end menu
-
-@node Sparc-Opts
-@section Options
-
-@cindex options for SPARC
-@cindex SPARC options
-@cindex architectures, SPARC
-@cindex SPARC architectures
-The SPARC chip family includes several successive levels (or other
-variants) of chip, using the same core instruction set, but including
-a few additional instructions at each level.
-
-By default, @code{@value{AS}} assumes the core instruction set (SPARC
-v6), but ``bumps'' the architecture level as needed: it switches to
-successively higher architectures as it encounters instructions that
-only exist in the higher levels.
-
-@table @code
-@item -Av6 | -Av7 | -Av8 | -Asparclite
-@kindex -Av6
-@kindex Av7
-@kindex -Av8
-@kindex -Asparclite
-Use one of the @samp{-A} options to select one of the SPARC
-architectures explicitly. If you select an architecture explicitly,
-@code{@value{AS}} reports a fatal error if it encounters an instruction
-or feature requiring a higher level.
-
-@item -bump
-Permit the assembler to ``bump'' the architecture level as required, but
-warn whenever it is necessary to switch to another level.
-@end table
-
-@ignore
-@c FIXME: (sparc) Fill in "syntax" section!
-@c subsection syntax
-I don't know anything about Sparc syntax. Someone who does
-will have to write this section.
-@end ignore
-
-@node Sparc-Float
-@section Floating Point
-
-@cindex floating point, SPARC (@sc{ieee})
-@cindex SPARC floating point (@sc{ieee})
-The Sparc uses @sc{ieee} floating-point numbers.
-
-@node Sparc-Directives
-@section Sparc Machine Directives
-
-@cindex SPARC machine directives
-@cindex machine directives, SPARC
-The Sparc version of @code{@value{AS}} supports the following additional
-machine directives:
-
-@table @code
-@item .common
-@cindex @code{common} directive, SPARC
-This must be followed by a symbol name, a positive number, and
-@code{"bss"}. This behaves somewhat like @code{.comm}, but the
-syntax is different.
-
-@item .half
-@cindex @code{half} directive, SPARC
-This is functionally identical to @code{.short}.
-
-@item .proc
-@cindex @code{proc} directive, SPARC
-This directive is ignored. Any text following it on the same
-line is also ignored.
-
-@item .reserve
-@cindex @code{reserve} directive, SPARC
-This must be followed by a symbol name, a positive number, and
-@code{"bss"}. This behaves somewhat like @code{.lcomm}, but the
-syntax is different.
-
-@item .seg
-@cindex @code{seg} directive, SPARC
-This must be followed by @code{"text"}, @code{"data"}, or
-@code{"data1"}. It behaves like @code{.text}, @code{.data}, or
-@code{.data 1}.
-
-@item .skip
-@cindex @code{skip} directive, SPARC
-This is functionally identical to the @code{.space} directive.
-
-@item .word
-@cindex @code{word} directive, SPARC
-On the Sparc, the .word directive produces 32 bit values,
-instead of the 16 bit values it produces on many other machines.
-@end table
-
-@end ifset
-@ifset I80386
-@ifset GENERIC
-@page
-@node i386-Dependent
-@chapter 80386 Dependent Features
-@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter 80386 Dependent Features
-@end ifclear
-
-@cindex i386 support
-@cindex i80306 support
-@menu
-* i386-Options:: Options
-* i386-Syntax:: AT&T Syntax versus Intel Syntax
-* i386-Opcodes:: Opcode Naming
-* i386-Regs:: Register Naming
-* i386-prefixes:: Opcode Prefixes
-* i386-Memory:: Memory References
-* i386-jumps:: Handling of Jump Instructions
-* i386-Float:: Floating Point
-* i386-Notes:: Notes
-@end menu
-
-@node i386-Options
-@section Options
-
-@cindex options for i386 (none)
-@cindex i386 options (none)
-The 80386 has no machine dependent options.
-
-@node i386-Syntax
-@section AT&T Syntax versus Intel Syntax
-
-@cindex i386 syntax compatibility
-@cindex syntax compatibility, i386
-In order to maintain compatibility with the output of @code{@value{GCC}},
-@code{@value{AS}} supports AT&T System V/386 assembler syntax. This is quite
-different from Intel syntax. We mention these differences because
-almost all 80386 documents used only Intel syntax. Notable differences
-between the two syntaxes are:
-
-@itemize @bullet
-@item
-@cindex immediate operands, i386
-@cindex i386 immediate operands
-@cindex register operands, i386
-@cindex i386 register operands
-@cindex jump/call operands, i386
-@cindex i386 jump/call operands
-@cindex operand delimiters, i386
-AT&T immediate operands are preceded by @samp{$}; Intel immediate
-operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
-AT&T register operands are preceded by @samp{%}; Intel register operands
-are undelimited. AT&T absolute (as opposed to PC relative) jump/call
-operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
-
-@item
-@cindex i386 source, destination operands
-@cindex source, destination operands; i386
-AT&T and Intel syntax use the opposite order for source and destination
-operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
-@samp{source, dest} convention is maintained for compatibility with
-previous Unix assemblers.
-
-@item
-@cindex opcode suffixes, i386
-@cindex sizes operands, i386
-@cindex i386 size suffixes
-In AT&T syntax the size of memory operands is determined from the last
-character of the opcode name. Opcode suffixes of @samp{b}, @samp{w},
-and @samp{l} specify byte (8-bit), word (16-bit), and long (32-bit)
-memory references. Intel syntax accomplishes this by prefixes memory
-operands (@emph{not} the opcodes themselves) with @samp{byte ptr},
-@samp{word ptr}, and @samp{dword ptr}. Thus, Intel @samp{mov al, byte
-ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T syntax.
-
-@item
-@cindex return instructions, i386
-@cindex i386 jump, call, return
-Immediate form long jumps and calls are
-@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
-Intel syntax is
-@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
-instruction
-is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
-@samp{ret far @var{stack-adjust}}.
-
-@item
-@cindex sections, i386
-@cindex i386 sections
-The AT&T assembler does not provide support for multiple section
-programs. Unix style systems expect all programs to be single sections.
-@end itemize
-
-@node i386-Opcodes
-@section Opcode Naming
-
-@cindex i386 opcode naming
-@cindex opcode naming, i386
-Opcode names are suffixed with one character modifiers which specify the
-size of operands. The letters @samp{b}, @samp{w}, and @samp{l} specify
-byte, word, and long operands. If no suffix is specified by an
-instruction and it contains no memory operands then @code{@value{AS}} tries to
-fill in the missing suffix based on the destination register operand
-(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
-to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
-@samp{movw $1, %bx}. Note that this is incompatible with the AT&T Unix
-assembler which assumes that a missing opcode suffix implies long
-operand size. (This incompatibility does not affect compiler output
-since compilers always explicitly specify the opcode suffix.)
-
-Almost all opcodes have the same names in AT&T and Intel format. There
-are a few exceptions. The sign extend and zero extend instructions need
-two sizes to specify them. They need a size to sign/zero extend
-@emph{from} and a size to zero extend @emph{to}. This is accomplished
-by using two opcode suffixes in AT&T syntax. Base names for sign extend
-and zero extend are @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T
-syntax (@samp{movsx} and @samp{movzx} in Intel syntax). The opcode
-suffixes are tacked on to this base name, the @emph{from} suffix before
-the @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
-``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
-thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
-and @samp{wl} (from word to long).
-
-@cindex conversion instructions, i386
-@cindex i386 conversion instructions
-The Intel-syntax conversion instructions
-
-@itemize @bullet
-@item
-@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
-
-@item
-@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
-
-@item
-@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
-
-@item
-@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
-@end itemize
-
-@noindent
-are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, and @samp{cltd} in
-AT&T naming. @code{@value{AS}} accepts either naming for these instructions.
-
-@cindex jump instructions, i386
-@cindex call instructions, i386
-Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
-AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
-convention.
-
-@node i386-Regs
-@section Register Naming
-
-@cindex i386 registers
-@cindex registers, i386
-Register operands are always prefixes with @samp{%}. The 80386 registers
-consist of
-
-@itemize @bullet
-@item
-the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
-@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
-frame pointer), and @samp{%esp} (the stack pointer).
-
-@item
-the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
-@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
-
-@item
-the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
-@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
-are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
-@samp{%cx}, and @samp{%dx})
-
-@item
-the 6 section registers @samp{%cs} (code section), @samp{%ds}
-(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
-and @samp{%gs}.
-
-@item
-the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
-@samp{%cr3}.
-
-@item
-the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
-@samp{%db3}, @samp{%db6}, and @samp{%db7}.
-
-@item
-the 2 test registers @samp{%tr6} and @samp{%tr7}.
-
-@item
-the 8 floating point register stack @samp{%st} or equivalently
-@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
-@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
-@end itemize
-
-@node i386-prefixes
-@section Opcode Prefixes
-
-@cindex i386 opcode prefixes
-@cindex opcode prefixes, i386
-@cindex prefixes, i386
-Opcode prefixes are used to modify the following opcode. They are used
-to repeat string instructions, to provide section overrides, to perform
-bus lock operations, and to give operand and address size (16-bit
-operands are specified in an instruction by prefixing what would
-normally be 32-bit operands with a ``operand size'' opcode prefix).
-Opcode prefixes are usually given as single-line instructions with no
-operands, and must directly precede the instruction they act upon. For
-example, the @samp{scas} (scan string) instruction is repeated with:
-@smallexample
- repne
- scas
-@end smallexample
-
-Here is a list of opcode prefixes: