* gas/config/tc-arm.c (arm_cpus): Add cortex-a15 entry.

[deliverable/binutils-gdb.git] / gas / doc / c-arm.texi

diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index cc4dd15a9a045ec4c97ed978fd2856255c0add80..478ede31a2331630d99eb928e778f0aa514e794d 100644 (file)
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -1,5 +1,5 @@
-@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2008
-@c Free Software Foundation, Inc.
+@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
+@c 2006, 2007, 2008, 2009  Free Software Foundation, Inc.

 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 


@@ -112,10 +112,15 @@ recognized:
 @code{arm1176jzf-s},
 @code{mpcore},
 @code{mpcorenovfp},
 @code{arm1176jzf-s},
 @code{mpcore},
 @code{mpcorenovfp},

+@code{cortex-a5},

 @code{cortex-a8},
 @code{cortex-a9},
 @code{cortex-a8},
 @code{cortex-a9},

+@code{cortex-a15},

 @code{cortex-r4},
 @code{cortex-r4},

+@code{cortex-r4f},

 @code{cortex-m3},
 @code{cortex-m3},

+@code{cortex-m1},
+@code{cortex-m0},

 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
 @code{i80200} (Intel XScale processor)
 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
 @code{i80200} (Intel XScale processor)
 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)


@@ -164,6 +169,7 @@ names are recognized:
 @code{armv7-a},
 @code{armv7-r},
 @code{armv7-m},
 @code{armv7-a},
 @code{armv7-r},
 @code{armv7-m},

+@code{armv7e-m},

 @code{iwmmxt}
 and
 @code{xscale}.
 @code{iwmmxt}
 and
 @code{xscale}.


@@ -196,15 +202,23 @@ The following format options are recognized:
 @code{vfp10-r0},
 @code{vfp9},
 @code{vfpxd},
 @code{vfp10-r0},
 @code{vfp9},
 @code{vfpxd},

-@code{vfpv2}
-@code{vfpv3}
-@code{vfpv3-d16}
+@code{vfpv2},
+@code{vfpv3},
+@code{vfpv3-fp16},
+@code{vfpv3-d16},
+@code{vfpv3-d16-fp16},
+@code{vfpv3xd},
+@code{vfpv3xd-d16},
+@code{vfpv4},
+@code{vfpv4-d16},
+@code{fpv4-sp-d16},

 @code{arm1020t},
 @code{arm1020e},
 @code{arm1136jf-s},
 @code{arm1020t},
 @code{arm1020e},
 @code{arm1136jf-s},

-@code{maverick}
+@code{maverick},
+@code{neon},

 and
 and

-@code{neon}.
+@code{neon-vfpv4}.

 
 In addition to determining which instructions are assembled, this option
 also affects the way in which the @code{.double} assembler directive behaves
 
 In addition to determining which instructions are assembled, this option
 also affects the way in which the @code{.double} assembler directive behaves


@@ -225,9 +239,29 @@ instructions; that is, it should behave as though the file starts with a
 This option specifies that the output generated by the assembler should
 be marked as supporting interworking.
 
 This option specifies that the output generated by the assembler should
 be marked as supporting interworking.
 

-@cindex @code{-mapcs} command line option, ARM
-@item -mapcs @code{[26|32]}
-This option specifies that the output generated by the assembler should
+@cindex @code{-mimplicit-it} command line option, ARM
+@item -mimplicit-it=never
+@itemx -mimplicit-it=always
+@itemx -mimplicit-it=arm
+@itemx -mimplicit-it=thumb
+The @code{-mimplicit-it} option controls the behavior of the assembler when
+conditional instructions are not enclosed in IT blocks.
+There are four possible behaviors.
+If @code{never} is specified, such constructs cause a warning in ARM
+code and an error in Thumb-2 code.
+If @code{always} is specified, such constructs are accepted in both
+ARM and Thumb-2 code, where the IT instruction is added implicitly.
+If @code{arm} is specified, such constructs are accepted in ARM code
+and cause an error in Thumb-2 code.
+If @code{thumb} is specified, such constructs cause a warning in ARM
+code and are accepted in Thumb-2 code.  If you omit this option, the
+behavior is equivalent to @code{-mimplicit-it=arm}.
+
+@cindex @code{-mapcs-26} command line option, ARM
+@cindex @code{-mapcs-32} command line option, ARM
+@item -mapcs-26
+@itemx -mapcs-32
+These options specify that the output generated by the assembler should

 be marked as supporting the indicated version of the Arm Procedure.
 Calling Standard.
 
 be marked as supporting the indicated version of the Arm Procedure.
 Calling Standard.
 


@@ -303,11 +337,48 @@ features.  The default is to warn.
 @node ARM Syntax
 @section Syntax
 @menu
 @node ARM Syntax
 @section Syntax
 @menu

+* ARM-Instruction-Set::      Instruction Set

 * ARM-Chars::                Special Characters
 * ARM-Regs::                 Register Names
 * ARM-Relocations::         Relocations
 * ARM-Chars::                Special Characters
 * ARM-Regs::                 Register Names
 * ARM-Relocations::         Relocations

+* ARM-Neon-Alignment::      NEON Alignment Specifiers

 @end menu
 
 @end menu
 

+@node ARM-Instruction-Set
+@subsection Instruction Set Syntax
+Two slightly different syntaxes are support for ARM and THUMB
+instructions.  The default, @code{divided}, uses the old style where
+ARM and THUMB instructions had their own, separate syntaxes.  The new,
+@code{unified} syntax, which can be selected via the @code{.syntax}
+directive, and has the following main features:
+
+@table @bullet
+@item
+Immediate operands do not require a @code{#} prefix.
+
+@item
+The @code{IT} instruction may appear, and if it does it is validated
+against subsequent conditional affixes.  In ARM mode it does not
+generate machine code, in THUMB mode it does.
+
+@item
+For ARM instructions the conditional affixes always appear at the end
+of the instruction.  For THUMB instructions conditional affixes can be
+used, but only inside the scope of an @code{IT} instruction.
+
+@item
+All of the instructions new to the V6T2 architecture (and later) are
+available.  (Only a few such instructions can be written in the
+@code{divided} syntax).
+
+@item
+The @code{.N} and @code{.W} suffixes are recognized and honored.
+
+@item
+All instructions set the flags if and only if they have an @code{s}
+affix.
+@end table
+

 @node ARM-Chars
 @subsection Special Characters
 
 @node ARM-Chars
 @subsection Special Characters
 


@@ -338,6 +409,21 @@ Either @samp{#} or @samp{$} can be used to indicate immediate operands.
 @cindex register names, ARM
 *TODO* Explain about ARM register naming, and the predefined names.
 
 @cindex register names, ARM
 *TODO* Explain about ARM register naming, and the predefined names.
 

+@node ARM-Neon-Alignment
+@subsection NEON Alignment Specifiers
+
+@cindex alignment for NEON instructions
+Some NEON load/store instructions allow an optional address
+alignment qualifier.
+The ARM documentation specifies that this is indicated by
+@samp{@@ @var{align}}. However GAS already interprets
+the @samp{@@} character as a "line comment" start,
+so @samp{: @var{align}} is used instead.  For example:
+
+@smallexample
+        vld1.8 @{q0@}, [r0, :128]
+@end smallexample
+

 @node ARM Floating Point
 @section Floating Point
 
 @node ARM Floating Point
 @section Floating Point
 


@@ -368,7 +454,8 @@ The following relocations are supported:
 @code{TLSGD},
 @code{TLSLDM},
 @code{TLSLDO},
 @code{TLSGD},
 @code{TLSLDM},
 @code{TLSLDO},

-@code{GOTTPOFF}
+@code{GOTTPOFF},
+@code{GOT_PREL}

 and
 @code{TPOFF}.
 
 and
 @code{TPOFF}.
 


@@ -453,7 +540,7 @@ for the @option{-mcpu} commandline option.
 
 @cindex @code{.dn} and @code{.qn} directives, ARM
 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
 
 @cindex @code{.dn} and @code{.qn} directives, ARM
 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]

-@item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
+@itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]

 
 The @code{dn} and @code{qn} directives are used to create typed
 and/or indexed register aliases for use in Advanced SIMD Extension
 
 The @code{dn} and @code{qn} directives are used to create typed
 and/or indexed register aliases for use in Advanced SIMD Extension


@@ -490,26 +577,31 @@ Set the EABI object attribute @var{tag} to @var{value}.
 The @var{tag} is either an attribute number, or one of the following:
 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
 The @var{tag} is either an attribute number, or one of the following:
 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},

-@code{Tag_THUMB_ISA_use}, @code{Tag_VFP_arch}, @code{Tag_WMMX_arch},
+@code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},

 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},

-@code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved},
+@code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},

 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},

-@code{Tag_VFP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
+@code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
+@code{Tag_MPextension_use}, @code{Tag_DIV_use},

 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
 @code{Tag_conformance}, @code{Tag_T2EE_use},
 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
 @code{Tag_conformance}, @code{Tag_T2EE_use},

-@code{Tag_Virtualization_use}, @code{Tag_MPextension_use}
+@code{Tag_Virtualization_use}

 
 The @var{value} is either a @code{number}, @code{"string"}, or
 @code{number, "string"} depending on the tag.
 
 
 The @var{value} is either a @code{number}, @code{"string"}, or
 @code{number, "string"} depending on the tag.
 

+Note - the following legacy values are also accepted by @var{tag}:
+@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed}, 
+@code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
+

 @cindex @code{.even} directive, ARM
 @item .even
 This directive aligns to an even-numbered address.
 @cindex @code{.even} directive, ARM
 @item .even
 This directive aligns to an even-numbered address.


@@ -562,6 +654,15 @@ Must be preceded by a @code{.personality} or @code{.personalityindex}
 directive.
 
 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 directive.
 
 @c IIIIIIIIIIIIIIIIIIIIIIIIII

+
+@cindex @code{.inst} directive, ARM
+@item .inst @var{opcode} [ , @dots{} ]
+@itemx .inst.n @var{opcode} [ , @dots{} ]
+@itemx .inst.w @var{opcode} [ , @dots{} ]
+Generates the instruction corresponding to the numerical value @var{opcode}.
+@code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
+specified explicitly, overriding the normal encoding rules.
+

 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 @c LLLLLLLLLLLLLLLLLLLLLLLLLL


@@ -675,7 +776,7 @@ or
 Make all unwinder annotations relative to a frame pointer.  Without this
 the unwinder will use offsets from the stack pointer.
 
 Make all unwinder annotations relative to a frame pointer.  Without this
 the unwinder will use offsets from the stack pointer.
 

-The syntax of this directive is the same as the @code{sub} or @code{mov}
+The syntax of this directive is the same as the @code{add} or @code{mov}

 instruction used to set the frame pointer.  @var{spreg} must be either
 @code{sp} or mentioned in a previous @code{.movsp} directive.
 
 instruction used to set the frame pointer.  @var{spreg} must be either
 @code{sp} or mentioned in a previous @code{.movsp} directive.
 


@@ -684,7 +785,7 @@ instruction used to set the frame pointer.  @var{spreg} must be either
 mov ip, sp
 @dots{}
 .setfp fp, ip, #4
 mov ip, sp
 @dots{}
 .setfp fp, ip, #4

-sub fp, ip, #4
+add fp, ip, #4

 @end smallexample
 
 @cindex @code{.secrel32} directive, ARM
 @end smallexample
 
 @cindex @code{.secrel32} directive, ARM


@@ -693,6 +794,11 @@ This directive emits relocations that evaluate to the section-relative
 offset of each expression's symbol.  This directive is only supported
 for PE targets.
 
 offset of each expression's symbol.  This directive is only supported
 for PE targets.
 

+@cindex @code{.syntax} directive, ARM
+@item .syntax [@code{unified} | @code{divided}]
+This directive sets the Instruction Set Syntax as described in the
+@ref{ARM-Instruction-Set} section.
+

 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 
 @cindex @code{.thumb} directive, ARM
 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 
 @cindex @code{.thumb} directive, ARM