+@table @code
+
+@item -mmcu
+selects the mcu architecture. If the architecture is 430Xv2 then this
+also enables NOP generation unless the @option{-mN} is also specified.
+
+@item -mcpu
+selects the cpu architecture. If the architecture is 430Xv2 then this
+also enables NOP generation unless the @option{-mN} is also specified.
+
+@item -msilicon-errata=@var{name}[,@var{name}@dots{}]
+Implements a fixup for named silicon errata. Multiple silicon errata
+can be specified by multiple uses of the @option{-msilicon-errata}
+option and/or by including the errata names, separated by commas, on
+an individual @option{-msilicon-errata} option. Errata names
+currently recognised by the assembler are:
+
+@table @code
+@item cpu4
+@code{PUSH #4} and @option{PUSH #8} need longer encodings on the
+MSP430. This option is enabled by default, and cannot be disabled.
+@item cpu8
+Do not set the @code{SP} to an odd value.
+@item cpu11
+Do not update the @code{SR} and the @code{PC} in the same instruction.
+@item cpu12
+Do not use the @code{PC} in a @code{CMP} or @code{BIT} instruction.
+@item cpu13
+Do not use an arithmetic instruction to modify the @code{SR}.
+@item cpu19
+Insert @code{NOP} after @code{CPUOFF}.
+@end table
+
+@item -msilicon-errata-warn=@var{name}[,@var{name}@dots{}]
+Like the @option{-msilicon-errata} option except that instead of
+fixing the specified errata, a warning message is issued instead.
+This option can be used alongside @option{-msilicon-errata} to
+generate messages whenever a problem is fixed, or on its own in order
+to inspect code for potential problems.
+
+@item -mP
+enables polymorph instructions handler.
+
+@item -mQ
+enables relaxation at assembly time. DANGEROUS!
+
+@item -ml
+indicates that the input uses the large code model.
+
+@item -mn
+enables the generation of a NOP instruction following any instruction
+that might change the interrupts enabled/disabled state. The
+pipelined nature of the MSP430 core means that any instruction that
+changes the interrupt state (@code{EINT}, @code{DINT}, @code{BIC #8,
+SR}, @code{BIS #8, SR} or @code{MOV.W <>, SR}) must be
+followed by a NOP instruction in order to ensure the correct
+processing of interrupts. By default it is up to the programmer to
+supply these NOP instructions, but this command line option enables
+the automatic insertion by the assembler, if they are missing.
+
+@item -mN
+disables the generation of a NOP instruction following any instruction
+that might change the interrupts enabled/disabled state. This is the
+default behaviour.
+
+@item -my
+tells the assembler to generate a warning message if a NOP does not
+immediately forllow an instruction that enables or disables
+interrupts. This is the default.
+
+Note that this option can be stacked with the @option{-mn} option so
+that the assembler will both warn about missing NOP instructions and
+then insert them automatically.
+
+@item -mY
+disables warnings about missing NOP instructions.
+
+@item -md
+mark the object file as one that requires data to copied from ROM to
+RAM at execution startup. Disabled by default.
+
+@end table