+2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
+
+ * gas/arm/armv8-a+rdma.d: New.
+ * gas/arm/armv8-a+rdma.s: New.
+
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+
+ * gas/arm/armv8-a+pan.d: New.
+ * gas/arm/armv8-a+pan.s: New.
+
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+
+ * gas/aarch64/rdma-directive.d: New.
+ * gas/aarch64/rdma.d: New.
+ * gas/aarch64/rdma.s: New.
+
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+
+ * gas/aarch64/lor-directive.d: New.
+ * gas/aarch64/lor.d: New.
+ * gas/aarch64/lor.s: New
+
+2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
+
+ * gas/aarch64/pan-directive.d: New.
+ * gas/aarch64/pan.d: New.
+ * gas/aarch64/pan.s: New
+
+2015-06-01 Jiong Wang <jiong.wang@arm.com>
+
+ * gas/aarch64/ilp32-basic.s: New testcase.
+ * gas/aarch64/ilp32-basic.d: Ditto.
+
+2015-06-01 Jiong Wang <jiong.wang@arm.com>
+
+ * gas/aarch64/reloc-insn.s: New testcase.
+ * gas/aarch64/reloc-insn.d: Ditto.
+
+2015-06-01 Jan Beulich <jbeulich@suse.com>
+
+ * gas/i386/avx512f.s: Adjust operand order for Intel syntax
+ vcvt{,u}si2ss.
+ * gas/i386/x86-64-avx512f.s: Adjust operand order for Intel
+ syntax vcvt{,u}si2s{d,s}.
+
+2015-06-01 Jan Beulich <jbeulich@suse.com>
+
+ * gas/i386/avx512f-intel.d: Adjust expectations on operand order.
+ * gas/i386/evex-lig256-intel.d: Likewise.
+ * gas/i386/evex-lig512-intel.d: Likewise.
+ * gas/i386/x86-64-avx512f-intel.d: Likewise.
+ * gas/i386/x86-64-evex-lig256-intel.d: Likewise.
+ * gas/i386/x86-64-evex-lig512-intel.d: Likewise.
+