-/* Extract a signed value from a bit field within an instruction
- encoding.
-
- INSN is the instruction opcode.
-
- WIDTH specifies the width of the bit field to extract (in bits).
-
- OFFSET specifies the least significant bit of the field where bits
- are numbered zero counting from least to most significant. */
-
-static int32_t
-extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset)
-{
- unsigned shift_l = sizeof (int32_t) * 8 - (offset + width);
- unsigned shift_r = sizeof (int32_t) * 8 - width;
-
- return ((int32_t) insn << shift_l) >> shift_r;
-}
-
-/* Determine if specified bits within an instruction opcode matches a
- specific pattern.
-
- INSN is the instruction opcode.
-
- MASK specifies the bits within the opcode that are to be tested
- agsinst for a match with PATTERN. */
-
-static int
-decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
-{
- return (insn & mask) == pattern;
-}
-
-/* Decode an opcode if it represents an immediate ADD or SUB instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- RD receives the 'rd' field from the decoded instruction.
- RN receives the 'rn' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-static int
-decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
- int32_t *imm)
-{
- if ((insn & 0x9f000000) == 0x91000000)
- {
- unsigned shift;
- unsigned op_is_sub;
-
- *rd = (insn >> 0) & 0x1f;
- *rn = (insn >> 5) & 0x1f;
- *imm = (insn >> 10) & 0xfff;
- shift = (insn >> 22) & 0x3;
- op_is_sub = (insn >> 30) & 0x1;
-
- switch (shift)
- {
- case 0:
- break;
- case 1:
- *imm <<= 12;
- break;
- default:
- /* UNDEFINED */
- return 0;
- }
-
- if (op_is_sub)
- *imm = -*imm;
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x add x%u, x%u, #%d\n",
- core_addr_to_string_nz (addr), insn, *rd, *rn,
- *imm);
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents an ADRP instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- RD receives the 'rd' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
-{
- if (decode_masked_match (insn, 0x9f000000, 0x90000000))
- {
- *rd = (insn >> 0) & 0x1f;
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x adrp x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents an branch immediate or branch
- and link immediate instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- LINK receives the 'link' bit from the decoded instruction.
- OFFSET receives the immediate offset from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_b (CORE_ADDR addr, uint32_t insn, unsigned *link, int32_t *offset)
-{
- /* b 0001 01ii iiii iiii iiii iiii iiii iiii */
- /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
- if (decode_masked_match (insn, 0x7c000000, 0x14000000))
- {
- *link = insn >> 31;
- *offset = extract_signed_bitfield (insn, 26, 0) << 2;
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *link ? "bl" : "b",
- core_addr_to_string_nz (addr + *offset));
-
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a conditional branch instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- COND receives the branch condition field from the decoded
- instruction.
- OFFSET receives the immediate offset from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
-{
- if (decode_masked_match (insn, 0xfe000000, 0x54000000))
- {
- *cond = (insn >> 0) & 0xf;
- *offset = extract_signed_bitfield (insn, 19, 5) << 2;
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x b<%u> 0x%s\n",
- core_addr_to_string_nz (addr), insn, *cond,
- core_addr_to_string_nz (addr + *offset));
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a branch via register instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- LINK receives the 'link' bit from the decoded instruction.
- RN receives the 'rn' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_br (CORE_ADDR addr, uint32_t insn, unsigned *link, unsigned *rn)
-{
- /* 8 4 0 6 2 8 4 0 */
- /* blr 110101100011111100000000000rrrrr */
- /* br 110101100001111100000000000rrrrr */
- if (decode_masked_match (insn, 0xffdffc1f, 0xd61f0000))
- {
- *link = (insn >> 21) & 1;
- *rn = (insn >> 5) & 0x1f;
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s 0x%x\n",
- core_addr_to_string_nz (addr), insn,
- *link ? "blr" : "br", *rn);
-
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a CBZ or CBNZ instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS64 receives the 'sf' field from the decoded instruction.
- OP receives the 'op' field from the decoded instruction.
- RN receives the 'rn' field from the decoded instruction.
- OFFSET receives the 'imm19' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_cb (CORE_ADDR addr,
- uint32_t insn, int *is64, unsigned *op, unsigned *rn,
- int32_t *offset)
-{
- if (decode_masked_match (insn, 0x7e000000, 0x34000000))
- {
- /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
- /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
-
- *rn = (insn >> 0) & 0x1f;
- *is64 = (insn >> 31) & 0x1;
- *op = (insn >> 24) & 0x1;
- *offset = extract_signed_bitfield (insn, 19, 5) << 2;
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *op ? "cbnz" : "cbz",
- core_addr_to_string_nz (addr + *offset));
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a ERET instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_eret (CORE_ADDR addr, uint32_t insn)
-{
- /* eret 1101 0110 1001 1111 0000 0011 1110 0000 */
- if (insn == 0xd69f03e0)
- {
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "decode: 0x%s 0x%x eret\n",
- core_addr_to_string_nz (addr), insn);
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a MOVZ instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- RD receives the 'rd' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
-{
- if (decode_masked_match (insn, 0xff800000, 0x52800000))
- {
- *rd = (insn >> 0) & 0x1f;
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x movz x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a ORR (shifted register)
- instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- RD receives the 'rd' field from the decoded instruction.
- RN receives the 'rn' field from the decoded instruction.
- RM receives the 'rm' field from the decoded instruction.
- IMM receives the 'imm6' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_orr_shifted_register_x (CORE_ADDR addr,
- uint32_t insn, unsigned *rd, unsigned *rn,
- unsigned *rm, int32_t *imm)
-{
- if (decode_masked_match (insn, 0xff200000, 0xaa000000))
- {
- *rd = (insn >> 0) & 0x1f;
- *rn = (insn >> 5) & 0x1f;
- *rm = (insn >> 16) & 0x1f;
- *imm = (insn >> 10) & 0x3f;
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x orr x%u, x%u, x%u, #%u\n",
- core_addr_to_string_nz (addr), insn, *rd,
- *rn, *rm, *imm);
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a RET instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- RN receives the 'rn' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
-{
- if (decode_masked_match (insn, 0xfffffc1f, 0xd65f0000))
- {
- *rn = (insn >> 5) & 0x1f;
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x ret x%u\n",
- core_addr_to_string_nz (addr), insn, *rn);
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents the following instruction:
- STP rt, rt2, [rn, #imm]
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- RT1 receives the 'rt' field from the decoded instruction.
- RT2 receives the 'rt2' field from the decoded instruction.
- RN receives the 'rn' field from the decoded instruction.
- IMM receives the 'imm' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_stp_offset (CORE_ADDR addr,
- uint32_t insn,
- unsigned *rt1, unsigned *rt2, unsigned *rn, int32_t *imm)
-{
- if (decode_masked_match (insn, 0xffc00000, 0xa9000000))
- {
- *rt1 = (insn >> 0) & 0x1f;
- *rn = (insn >> 5) & 0x1f;
- *rt2 = (insn >> 10) & 0x1f;
- *imm = extract_signed_bitfield (insn, 7, 15);
- *imm <<= 3;
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]\n",
- core_addr_to_string_nz (addr), insn,
- *rt1, *rt2, *rn, *imm);
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents the following instruction:
- STP rt, rt2, [rn, #imm]!
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- RT1 receives the 'rt' field from the decoded instruction.
- RT2 receives the 'rt2' field from the decoded instruction.
- RN receives the 'rn' field from the decoded instruction.
- IMM receives the 'imm' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_stp_offset_wb (CORE_ADDR addr,
- uint32_t insn,
- unsigned *rt1, unsigned *rt2, unsigned *rn,
- int32_t *imm)
-{
- if (decode_masked_match (insn, 0xffc00000, 0xa9800000))
- {
- *rt1 = (insn >> 0) & 0x1f;
- *rn = (insn >> 5) & 0x1f;
- *rt2 = (insn >> 10) & 0x1f;
- *imm = extract_signed_bitfield (insn, 7, 15);
- *imm <<= 3;
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]!\n",
- core_addr_to_string_nz (addr), insn,
- *rt1, *rt2, *rn, *imm);
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents the following instruction:
- STUR rt, [rn, #imm]
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS64 receives size field from the decoded instruction.
- RT receives the 'rt' field from the decoded instruction.
- RN receives the 'rn' field from the decoded instruction.
- IMM receives the 'imm' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
- unsigned *rn, int32_t *imm)
-{
- if (decode_masked_match (insn, 0xbfe00c00, 0xb8000000))
- {
- *is64 = (insn >> 30) & 1;
- *rt = (insn >> 0) & 0x1f;
- *rn = (insn >> 5) & 0x1f;
- *imm = extract_signed_bitfield (insn, 9, 12);
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x stur %c%u, [x%u + #%d]\n",
- core_addr_to_string_nz (addr), insn,
- *is64 ? 'x' : 'w', *rt, *rn, *imm);
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a TB or TBNZ instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- OP receives the 'op' field from the decoded instruction.
- BIT receives the bit position field from the decoded instruction.
- RT receives 'rt' field from the decoded instruction.
- IMM receives 'imm' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_tb (CORE_ADDR addr,
- uint32_t insn, unsigned *op, unsigned *bit, unsigned *rt,
- int32_t *imm)
-{
- if (decode_masked_match (insn, 0x7e000000, 0x36000000))
- {
- /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
- /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
-
- *rt = (insn >> 0) & 0x1f;
- *op = insn & (1 << 24);
- *bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f);
- *imm = extract_signed_bitfield (insn, 14, 5) << 2;
-
- if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *op ? "tbnz" : "tbz", *rt, *bit,
- core_addr_to_string_nz (addr + *imm));
- return 1;
- }
- return 0;
-}
-