+static struct cris_unwind_cache *
+cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
+ void **this_cache)
+{
+ struct gdbarch *gdbarch = get_frame_arch (this_frame);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ struct cris_unwind_cache *info;
+ CORE_ADDR pc;
+ CORE_ADDR sp;
+ CORE_ADDR addr;
+ char buf[4];
+ int i;
+
+ if ((*this_cache))
+ return (*this_cache);
+
+ info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
+ (*this_cache) = info;
+ info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
+
+ /* Zero all fields. */
+ info->prev_sp = 0;
+ info->base = 0;
+ info->size = 0;
+ info->sp_offset = 0;
+ info->r8_offset = 0;
+ info->uses_frame = 0;
+ info->return_pc = 0;
+ info->leaf_function = 0;
+
+ get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
+ info->base = extract_unsigned_integer (buf, 4);
+
+ addr = cris_sigcontext_addr (this_frame);
+
+ /* Layout of the sigcontext struct:
+ struct sigcontext {
+ struct pt_regs regs;
+ unsigned long oldmask;
+ unsigned long usp;
+ }; */
+
+ if (tdep->cris_version == 10)
+ {
+ /* R0 to R13 are stored in reverse order at offset (2 * 4) in
+ struct pt_regs. */
+ for (i = 0; i <= 13; i++)
+ info->saved_regs[i].addr = addr + ((15 - i) * 4);
+
+ info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
+ info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
+ info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
+ /* Note: IRP is off by 2 at this point. There's no point in correcting
+ it though since that will mean that the backtrace will show a PC
+ different from what is shown when stopped. */
+ info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
+ info->saved_regs[gdbarch_pc_regnum (gdbarch)]
+ = info->saved_regs[IRP_REGNUM];
+ info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
+ }
+ else
+ {
+ /* CRISv32. */
+ /* R0 to R13 are stored in order at offset (1 * 4) in
+ struct pt_regs. */
+ for (i = 0; i <= 13; i++)
+ info->saved_regs[i].addr = addr + ((i + 1) * 4);
+
+ info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
+ info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
+ info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
+ info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
+ info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
+ info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
+ info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
+ info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
+ info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
+
+ /* FIXME: If ERP is in a delay slot at this point then the PC will
+ be wrong at this point. This problem manifests itself in the
+ sigaltstack.exp test case, which occasionally generates FAILs when
+ the signal is received while in a delay slot.
+
+ This could be solved by a couple of read_memory_unsigned_integer and a
+ trad_frame_set_value. */
+ info->saved_regs[gdbarch_pc_regnum (gdbarch)]
+ = info->saved_regs[ERP_REGNUM];
+
+ info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
+ = addr + (25 * 4);
+ }
+
+ return info;
+}
+
+static void
+cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
+ struct frame_id *this_id)
+{
+ struct cris_unwind_cache *cache =
+ cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
+ (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
+}
+
+/* Forward declaration. */
+
+static struct value *cris_frame_prev_register (struct frame_info *this_frame,
+ void **this_cache, int regnum);
+static struct value *
+cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
+ void **this_cache, int regnum)
+{
+ /* Make sure we've initialized the cache. */
+ cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
+ return cris_frame_prev_register (this_frame, this_cache, regnum);
+}
+
+static int
+cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
+ struct frame_info *this_frame,
+ void **this_cache)
+{
+ if (cris_sigtramp_start (this_frame)
+ || cris_rt_sigtramp_start (this_frame))
+ return 1;
+
+ return 0;
+}
+
+static const struct frame_unwind cris_sigtramp_frame_unwind =
+{
+ SIGTRAMP_FRAME,
+ cris_sigtramp_frame_this_id,
+ cris_sigtramp_frame_prev_register,
+ NULL,
+ cris_sigtramp_frame_sniffer
+};
+
+static int
+crisv32_single_step_through_delay (struct gdbarch *gdbarch,
+ struct frame_info *this_frame)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ ULONGEST erp;
+ int ret = 0;
+
+ if (tdep->cris_mode == cris_mode_guru)
+ erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
+ else
+ erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
+
+ if (erp & 0x1)
+ {
+ /* In delay slot - check if there's a breakpoint at the preceding
+ instruction. */
+ if (breakpoint_here_p (erp & ~0x1))
+ ret = 1;
+ }
+ return ret;
+}
+
+/* Hardware watchpoint support. */
+
+/* We support 6 hardware data watchpoints, but cannot trigger on execute
+ (any combination of read/write is fine). */
+
+int
+cris_can_use_hardware_watchpoint (int type, int count, int other)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
+
+ /* No bookkeeping is done here; it is handled by the remote debug agent. */
+
+ if (tdep->cris_version != 32)
+ return 0;
+ else
+ /* CRISv32: Six data watchpoints, one for instructions. */
+ return (((type == bp_read_watchpoint || type == bp_access_watchpoint
+ || type == bp_hardware_watchpoint) && count <= 6)
+ || (type == bp_hardware_breakpoint && count <= 1));
+}
+
+/* The CRISv32 hardware data watchpoints work by specifying ranges,
+ which have no alignment or length restrictions. */
+
+int
+cris_region_ok_for_watchpoint (CORE_ADDR addr, int len)
+{
+ return 1;
+}
+
+/* If the inferior has some watchpoint that triggered, return the
+ address associated with that watchpoint. Otherwise, return
+ zero. */
+
+CORE_ADDR
+cris_stopped_data_address (void)
+{
+ CORE_ADDR eda;
+ eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM);
+ return eda;
+}
+