+ else
+ {
+ d10v_frame_init_saved_regs (fi);
+ }
+}
+
+static void
+show_regs (char *args, int from_tty)
+{
+ int a;
+ printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
+ (long) read_register (PC_REGNUM),
+ (long) d10v_make_iaddr (read_register (PC_REGNUM)),
+ (long) read_register (PSW_REGNUM),
+ (long) read_register (24),
+ (long) read_register (25),
+ (long) read_register (23));
+ printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
+ (long) read_register (0),
+ (long) read_register (1),
+ (long) read_register (2),
+ (long) read_register (3),
+ (long) read_register (4),
+ (long) read_register (5),
+ (long) read_register (6),
+ (long) read_register (7));
+ printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
+ (long) read_register (8),
+ (long) read_register (9),
+ (long) read_register (10),
+ (long) read_register (11),
+ (long) read_register (12),
+ (long) read_register (13),
+ (long) read_register (14),
+ (long) read_register (15));
+ for (a = 0; a < NR_IMAP_REGS; a++)
+ {
+ if (a > 0)
+ printf_filtered (" ");
+ printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a));
+ }
+ if (NR_DMAP_REGS == 1)
+ printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
+ else
+ {
+ for (a = 0; a < NR_DMAP_REGS; a++)
+ {
+ printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a));
+ }
+ printf_filtered ("\n");
+ }
+ printf_filtered ("A0-A%d", NR_A_REGS - 1);
+ for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++)
+ {
+ char num[MAX_REGISTER_RAW_SIZE];
+ int i;
+ printf_filtered (" ");
+ read_register_gen (a, (char *) &num);
+ for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++)
+ {
+ printf_filtered ("%02x", (num[i] & 0xff));
+ }
+ }
+ printf_filtered ("\n");
+}
+
+static CORE_ADDR
+d10v_read_pc (ptid_t ptid)
+{
+ ptid_t save_ptid;
+ CORE_ADDR pc;
+ CORE_ADDR retval;
+
+ save_ptid = inferior_ptid;
+ inferior_ptid = ptid;
+ pc = (int) read_register (PC_REGNUM);
+ inferior_ptid = save_ptid;
+ retval = d10v_make_iaddr (pc);
+ return retval;
+}
+
+static void
+d10v_write_pc (CORE_ADDR val, ptid_t ptid)
+{
+ ptid_t save_ptid;
+
+ save_ptid = inferior_ptid;
+ inferior_ptid = ptid;
+ write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val));
+ inferior_ptid = save_ptid;
+}
+
+static CORE_ADDR
+d10v_read_sp (void)
+{
+ return (d10v_make_daddr (read_register (SP_REGNUM)));
+}
+
+static void
+d10v_write_sp (CORE_ADDR val)
+{
+ write_register (SP_REGNUM, d10v_convert_daddr_to_raw (val));
+}
+
+static void
+d10v_write_fp (CORE_ADDR val)
+{
+ write_register (FP_REGNUM, d10v_convert_daddr_to_raw (val));
+}
+
+static CORE_ADDR
+d10v_read_fp (void)
+{
+ return (d10v_make_daddr (read_register (FP_REGNUM)));
+}
+
+/* Function: push_return_address (pc)
+ Set up the return address for the inferior function call.
+ Needed for targets where we don't actually execute a JSR/BSR instruction */
+
+static CORE_ADDR
+d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
+{
+ write_register (LR_REGNUM, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
+ return sp;
+}
+
+
+/* When arguments must be pushed onto the stack, they go on in reverse
+ order. The below implements a FILO (stack) to do this. */
+
+struct stack_item
+{
+ int len;
+ struct stack_item *prev;
+ void *data;
+};
+
+static struct stack_item *push_stack_item (struct stack_item *prev,
+ void *contents, int len);
+static struct stack_item *
+push_stack_item (struct stack_item *prev, void *contents, int len)
+{
+ struct stack_item *si;
+ si = xmalloc (sizeof (struct stack_item));
+ si->data = xmalloc (len);
+ si->len = len;
+ si->prev = prev;
+ memcpy (si->data, contents, len);
+ return si;
+}
+
+static struct stack_item *pop_stack_item (struct stack_item *si);
+static struct stack_item *
+pop_stack_item (struct stack_item *si)
+{
+ struct stack_item *dead = si;
+ si = si->prev;
+ xfree (dead->data);
+ xfree (dead);
+ return si;
+}
+
+
+static CORE_ADDR
+d10v_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
+{
+ int i;
+ int regnum = ARG1_REGNUM;
+ struct stack_item *si = NULL;
+
+ /* Fill in registers and arg lists */
+ for (i = 0; i < nargs; i++)
+ {
+ struct value *arg = args[i];
+ struct type *type = check_typedef (VALUE_TYPE (arg));
+ char *contents = VALUE_CONTENTS (arg);
+ int len = TYPE_LENGTH (type);
+ /* printf ("push: type=%d len=%d\n", type->code, len); */
+ {
+ int aligned_regnum = (regnum + 1) & ~1;
+ if (len <= 2 && regnum <= ARGN_REGNUM)
+ /* fits in a single register, do not align */
+ {
+ long val = extract_unsigned_integer (contents, len);
+ write_register (regnum++, val);
+ }
+ else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2)
+ /* value fits in remaining registers, store keeping left
+ aligned */
+ {
+ int b;
+ regnum = aligned_regnum;
+ for (b = 0; b < (len & ~1); b += 2)
+ {
+ long val = extract_unsigned_integer (&contents[b], 2);
+ write_register (regnum++, val);
+ }
+ if (b < len)
+ {
+ long val = extract_unsigned_integer (&contents[b], 1);
+ write_register (regnum++, (val << 8));
+ }
+ }
+ else
+ {
+ /* arg will go onto stack */
+ regnum = ARGN_REGNUM + 1;
+ si = push_stack_item (si, contents, len);
+ }
+ }
+ }
+
+ while (si)
+ {
+ sp = (sp - si->len) & ~1;
+ write_memory (sp, si->data, si->len);
+ si = pop_stack_item (si);
+ }
+
+ return sp;
+}
+
+
+/* Given a return value in `regbuf' with a type `valtype',
+ extract and copy its value into `valbuf'. */
+
+static void
+d10v_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES],
+ char *valbuf)
+{
+ int len;
+ /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */
+ {
+ len = TYPE_LENGTH (type);
+ if (len == 1)
+ {
+ unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM));
+ store_unsigned_integer (valbuf, 1, c);
+ }
+ else if ((len & 1) == 0)
+ memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len);
+ else
+ {
+ /* For return values of odd size, the first byte is in the
+ least significant part of the first register. The
+ remaining bytes in remaining registers. Interestingly,
+ when such values are passed in, the last byte is in the
+ most significant byte of that same register - wierd. */
+ memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len);
+ }
+ }
+}
+
+/* Translate a GDB virtual ADDR/LEN into a format the remote target
+ understands. Returns number of bytes that can be transfered
+ starting at TARG_ADDR. Return ZERO if no bytes can be transfered
+ (segmentation fault). Since the simulator knows all about how the
+ VM system works, we just call that to do the translation. */
+
+static void
+remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes,
+ CORE_ADDR *targ_addr, int *targ_len)
+{
+ long out_addr;
+ long out_len;
+ out_len = sim_d10v_translate_addr (memaddr, nr_bytes,
+ &out_addr,
+ d10v_dmap_register,
+ d10v_imap_register);
+ *targ_addr = out_addr;
+ *targ_len = out_len;
+}
+
+
+/* The following code implements access to, and display of, the D10V's
+ instruction trace buffer. The buffer consists of 64K or more
+ 4-byte words of data, of which each words includes an 8-bit count,
+ an 8-bit segment number, and a 16-bit instruction address.
+
+ In theory, the trace buffer is continuously capturing instruction
+ data that the CPU presents on its "debug bus", but in practice, the
+ ROMified GDB stub only enables tracing when it continues or steps
+ the program, and stops tracing when the program stops; so it
+ actually works for GDB to read the buffer counter out of memory and
+ then read each trace word. The counter records where the tracing
+ stops, but there is no record of where it started, so we remember
+ the PC when we resumed and then search backwards in the trace
+ buffer for a word that includes that address. This is not perfect,
+ because you will miss trace data if the resumption PC is the target
+ of a branch. (The value of the buffer counter is semi-random, any
+ trace data from a previous program stop is gone.) */
+
+/* The address of the last word recorded in the trace buffer. */
+
+#define DBBC_ADDR (0xd80000)
+
+/* The base of the trace buffer, at least for the "Board_0". */
+
+#define TRACE_BUFFER_BASE (0xf40000)
+
+static void trace_command (char *, int);
+
+static void untrace_command (char *, int);
+
+static void trace_info (char *, int);
+
+static void tdisassemble_command (char *, int);
+
+static void display_trace (int, int);
+
+/* True when instruction traces are being collected. */
+
+static int tracing;
+
+/* Remembered PC. */
+
+static CORE_ADDR last_pc;
+
+/* True when trace output should be displayed whenever program stops. */
+
+static int trace_display;
+
+/* True when trace listing should include source lines. */
+
+static int default_trace_show_source = 1;
+
+struct trace_buffer
+ {
+ int size;
+ short *counts;
+ CORE_ADDR *addrs;
+ }
+trace_data;
+
+static void
+trace_command (char *args, int from_tty)
+{
+ /* Clear the host-side trace buffer, allocating space if needed. */
+ trace_data.size = 0;
+ if (trace_data.counts == NULL)
+ trace_data.counts = (short *) xmalloc (65536 * sizeof (short));
+ if (trace_data.addrs == NULL)
+ trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR));
+
+ tracing = 1;
+
+ printf_filtered ("Tracing is now on.\n");
+}
+
+static void
+untrace_command (char *args, int from_tty)
+{
+ tracing = 0;
+
+ printf_filtered ("Tracing is now off.\n");
+}
+
+static void
+trace_info (char *args, int from_tty)
+{
+ int i;
+
+ if (trace_data.size)
+ {
+ printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
+
+ for (i = 0; i < trace_data.size; ++i)
+ {
+ printf_filtered ("%d: %d instruction%s at 0x%s\n",
+ i,
+ trace_data.counts[i],
+ (trace_data.counts[i] == 1 ? "" : "s"),
+ paddr_nz (trace_data.addrs[i]));
+ }
+ }
+ else
+ printf_filtered ("No entries in trace buffer.\n");
+
+ printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
+}
+
+/* Print the instruction at address MEMADDR in debugged memory,
+ on STREAM. Returns length of the instruction, in bytes. */
+
+static int
+print_insn (CORE_ADDR memaddr, struct ui_file *stream)
+{
+ /* If there's no disassembler, something is very wrong. */
+ if (tm_print_insn == NULL)
+ internal_error (__FILE__, __LINE__,
+ "print_insn: no disassembler");
+
+ if (TARGET_BYTE_ORDER == BIG_ENDIAN)
+ tm_print_insn_info.endian = BFD_ENDIAN_BIG;
+ else
+ tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
+ return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info);
+}
+
+static void
+d10v_eva_prepare_to_trace (void)
+{
+ if (!tracing)
+ return;
+
+ last_pc = read_register (PC_REGNUM);
+}
+
+/* Collect trace data from the target board and format it into a form
+ more useful for display. */
+
+static void
+d10v_eva_get_trace_data (void)
+{
+ int count, i, j, oldsize;
+ int trace_addr, trace_seg, trace_cnt, next_cnt;
+ unsigned int last_trace, trace_word, next_word;
+ unsigned int *tmpspace;
+
+ if (!tracing)
+ return;
+
+ tmpspace = xmalloc (65536 * sizeof (unsigned int));
+
+ last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
+
+ /* Collect buffer contents from the target, stopping when we reach
+ the word recorded when execution resumed. */
+
+ count = 0;
+ while (last_trace > 0)
+ {
+ QUIT;
+ trace_word =
+ read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
+ trace_addr = trace_word & 0xffff;
+ last_trace -= 4;
+ /* Ignore an apparently nonsensical entry. */
+ if (trace_addr == 0xffd5)
+ continue;
+ tmpspace[count++] = trace_word;
+ if (trace_addr == last_pc)
+ break;
+ if (count > 65535)
+ break;
+ }
+
+ /* Move the data to the host-side trace buffer, adjusting counts to
+ include the last instruction executed and transforming the address
+ into something that GDB likes. */
+
+ for (i = 0; i < count; ++i)
+ {
+ trace_word = tmpspace[i];
+ next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
+ trace_addr = trace_word & 0xffff;
+ next_cnt = (next_word >> 24) & 0xff;
+ j = trace_data.size + count - i - 1;
+ trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
+ trace_data.counts[j] = next_cnt + 1;
+ }
+
+ oldsize = trace_data.size;
+ trace_data.size += count;
+
+ xfree (tmpspace);
+
+ if (trace_display)
+ display_trace (oldsize, trace_data.size);
+}
+
+static void
+tdisassemble_command (char *arg, int from_tty)
+{
+ int i, count;
+ CORE_ADDR low, high;
+ char *space_index;
+
+ if (!arg)
+ {
+ low = 0;
+ high = trace_data.size;
+ }
+ else if (!(space_index = (char *) strchr (arg, ' ')))
+ {
+ low = parse_and_eval_address (arg);
+ high = low + 5;
+ }
+ else
+ {
+ /* Two arguments. */
+ *space_index = '\0';
+ low = parse_and_eval_address (arg);
+ high = parse_and_eval_address (space_index + 1);
+ if (high < low)
+ high = low;
+ }
+
+ printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high));
+
+ display_trace (low, high);
+
+ printf_filtered ("End of trace dump.\n");
+ gdb_flush (gdb_stdout);
+}
+
+static void
+display_trace (int low, int high)
+{
+ int i, count, trace_show_source, first, suppress;
+ CORE_ADDR next_address;
+
+ trace_show_source = default_trace_show_source;
+ if (!have_full_symbols () && !have_partial_symbols ())
+ {
+ trace_show_source = 0;
+ printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
+ printf_filtered ("Trace will not display any source.\n");
+ }
+
+ first = 1;
+ suppress = 0;
+ for (i = low; i < high; ++i)
+ {
+ next_address = trace_data.addrs[i];
+ count = trace_data.counts[i];
+ while (count-- > 0)
+ {
+ QUIT;
+ if (trace_show_source)
+ {
+ struct symtab_and_line sal, sal_prev;
+
+ sal_prev = find_pc_line (next_address - 4, 0);
+ sal = find_pc_line (next_address, 0);
+
+ if (sal.symtab)
+ {
+ if (first || sal.line != sal_prev.line)
+ print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
+ suppress = 0;
+ }
+ else
+ {
+ if (!suppress)
+ /* FIXME-32x64--assumes sal.pc fits in long. */
+ printf_filtered ("No source file for address %s.\n",
+ local_hex_string ((unsigned long) sal.pc));
+ suppress = 1;
+ }
+ }
+ first = 0;
+ print_address (next_address, gdb_stdout);
+ printf_filtered (":");
+ printf_filtered ("\t");
+ wrap_here (" ");
+ next_address = next_address + print_insn (next_address, gdb_stdout);
+ printf_filtered ("\n");
+ gdb_flush (gdb_stdout);
+ }
+ }
+}
+
+
+static gdbarch_init_ftype d10v_gdbarch_init;
+
+static struct gdbarch *
+d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+{
+ static LONGEST d10v_call_dummy_words[] =
+ {0};
+ struct gdbarch *gdbarch;
+ int d10v_num_regs;
+ struct gdbarch_tdep *tdep;
+ gdbarch_register_name_ftype *d10v_register_name;
+ gdbarch_register_sim_regno_ftype *d10v_register_sim_regno;
+
+ /* Find a candidate among the list of pre-declared architectures. */
+ arches = gdbarch_list_lookup_by_info (arches, &info);
+ if (arches != NULL)
+ return arches->gdbarch;
+
+ /* None found, create a new architecture from the information
+ provided. */
+ tdep = XMALLOC (struct gdbarch_tdep);
+ gdbarch = gdbarch_alloc (&info, tdep);
+
+ switch (info.bfd_arch_info->mach)
+ {
+ case bfd_mach_d10v_ts2:
+ d10v_num_regs = 37;
+ d10v_register_name = d10v_ts2_register_name;
+ d10v_register_sim_regno = d10v_ts2_register_sim_regno;
+ tdep->a0_regnum = TS2_A0_REGNUM;
+ tdep->nr_dmap_regs = TS2_NR_DMAP_REGS;
+ tdep->dmap_register = d10v_ts2_dmap_register;
+ tdep->imap_register = d10v_ts2_imap_register;
+ break;
+ default:
+ case bfd_mach_d10v_ts3:
+ d10v_num_regs = 42;
+ d10v_register_name = d10v_ts3_register_name;
+ d10v_register_sim_regno = d10v_ts3_register_sim_regno;
+ tdep->a0_regnum = TS3_A0_REGNUM;
+ tdep->nr_dmap_regs = TS3_NR_DMAP_REGS;
+ tdep->dmap_register = d10v_ts3_dmap_register;
+ tdep->imap_register = d10v_ts3_imap_register;
+ break;
+ }
+
+ set_gdbarch_read_pc (gdbarch, d10v_read_pc);
+ set_gdbarch_write_pc (gdbarch, d10v_write_pc);
+ set_gdbarch_read_fp (gdbarch, d10v_read_fp);
+ set_gdbarch_write_fp (gdbarch, d10v_write_fp);
+ set_gdbarch_read_sp (gdbarch, d10v_read_sp);
+ set_gdbarch_write_sp (gdbarch, d10v_write_sp);
+
+ set_gdbarch_num_regs (gdbarch, d10v_num_regs);
+ set_gdbarch_sp_regnum (gdbarch, 15);
+ set_gdbarch_fp_regnum (gdbarch, 11);
+ set_gdbarch_pc_regnum (gdbarch, 18);
+ set_gdbarch_register_name (gdbarch, d10v_register_name);
+ set_gdbarch_register_size (gdbarch, 2);
+ set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16);
+ set_gdbarch_register_byte (gdbarch, d10v_register_byte);
+ set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size);
+ set_gdbarch_max_register_raw_size (gdbarch, 8);
+ set_gdbarch_register_virtual_size (gdbarch, generic_register_virtual_size);
+ set_gdbarch_max_register_virtual_size (gdbarch, 8);
+ set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type);
+
+ set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT);
+ set_gdbarch_addr_bit (gdbarch, 32);
+ set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer);
+ set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address);
+ set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address);
+ set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
+ set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT);
+ set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
+ set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+ /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
+ double'' is 64 bits. */
+ set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
+ set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
+ set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+ switch (info.byte_order)
+ {
+ case BIG_ENDIAN:
+ set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
+ set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big);
+ set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
+ break;
+ case LITTLE_ENDIAN:
+ set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
+ set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little);
+ set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little);
+ break;
+ default:
+ internal_error (__FILE__, __LINE__,
+ "d10v_gdbarch_init: bad byte order for float format");
+ }
+
+ set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
+ set_gdbarch_call_dummy_length (gdbarch, 0);
+ set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
+ set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
+ set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
+ set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
+ set_gdbarch_call_dummy_start_offset (gdbarch, 0);
+ set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
+ set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words);
+ set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words));
+ set_gdbarch_call_dummy_p (gdbarch, 1);
+ set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
+ set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
+ set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
+
+ set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value);
+ set_gdbarch_push_arguments (gdbarch, d10v_push_arguments);
+ set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
+ set_gdbarch_push_return_address (gdbarch, d10v_push_return_address);
+
+ set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return);
+ set_gdbarch_store_return_value (gdbarch, d10v_store_return_value);
+ set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address);
+ set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention);
+
+ set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs);
+ set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info);
+
+ set_gdbarch_pop_frame (gdbarch, d10v_pop_frame);
+
+ set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue);
+ set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+ set_gdbarch_decr_pc_after_break (gdbarch, 4);
+ set_gdbarch_function_start_offset (gdbarch, 0);
+ set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc);
+
+ set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address);
+
+ set_gdbarch_frame_args_skip (gdbarch, 0);
+ set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
+ set_gdbarch_frame_chain (gdbarch, d10v_frame_chain);
+ set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid);
+ set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc);
+ set_gdbarch_frame_args_address (gdbarch, default_frame_address);
+ set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
+ set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call);
+ set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
+ set_gdbarch_stack_align (gdbarch, d10v_stack_align);
+
+ set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno);
+ set_gdbarch_extra_stack_alignment_needed (gdbarch, 0);
+
+ return gdbarch;
+}
+
+
+extern void (*target_resume_hook) (void);
+extern void (*target_wait_loop_hook) (void);
+
+void
+_initialize_d10v_tdep (void)
+{
+ register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init);
+
+ tm_print_insn = print_insn_d10v;
+
+ target_resume_hook = d10v_eva_prepare_to_trace;
+ target_wait_loop_hook = d10v_eva_get_trace_data;
+
+ add_com ("regs", class_vars, show_regs, "Print all registers");
+
+ add_com ("itrace", class_support, trace_command,
+ "Enable tracing of instruction execution.");
+
+ add_com ("iuntrace", class_support, untrace_command,
+ "Disable tracing of instruction execution.");
+
+ add_com ("itdisassemble", class_vars, tdisassemble_command,
+ "Disassemble the trace buffer.\n\
+Two optional arguments specify a range of trace buffer entries\n\
+as reported by info trace (NOT addresses!).");
+
+ add_info ("itrace", trace_info,
+ "Display info about the trace data buffer.");
+
+ add_show_from_set (add_set_cmd ("itracedisplay", no_class,
+ var_integer, (char *) &trace_display,
+ "Set automatic display of trace.\n", &setlist),
+ &showlist);
+ add_show_from_set (add_set_cmd ("itracesource", no_class,
+ var_integer, (char *) &default_trace_show_source,
+ "Set display of source code with trace.\n", &setlist),
+ &showlist);