Fix aarch64 ftrace JIT condition testcase

[deliverable/binutils-gdb.git] / gdb / features / arm-core.xml

diff --git a/gdb/features/arm-core.xml b/gdb/features/arm-core.xml
index c2718f5eea7e5d23e911253dc4e041f7ce46d92d..f7f1a1d3ed36ee99b6e2e3b1d32ead6b58d42489 100644 (file)
--- a/gdb/features/arm-core.xml
+++ b/gdb/features/arm-core.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <?xml version="1.0"?>

-<!-- Copyright (C) 2007 Free Software Foundation, Inc.
+<!-- Copyright (C) 2007-2016 Free Software Foundation, Inc.

 
      Copying and distribution of this file, with or without modification,
      are permitted in any medium without royalty provided the copyright
 
      Copying and distribution of this file, with or without modification,
      are permitted in any medium without royalty provided the copyright


@@ -7,22 +7,22 @@
 
 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
 <feature name="org.gnu.gdb.arm.core">
 
 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
 <feature name="org.gnu.gdb.arm.core">

-  <reg name="r0" bitsize="32"/>
-  <reg name="r1" bitsize="32"/>
-  <reg name="r2" bitsize="32"/>
-  <reg name="r3" bitsize="32"/>
-  <reg name="r4" bitsize="32"/>
-  <reg name="r5" bitsize="32"/>
-  <reg name="r6" bitsize="32"/>
-  <reg name="r7" bitsize="32"/>
-  <reg name="r8" bitsize="32"/>
-  <reg name="r9" bitsize="32"/>
-  <reg name="r10" bitsize="32"/>
-  <reg name="r11" bitsize="32"/>
-  <reg name="r12" bitsize="32"/>
-  <reg name="sp" bitsize="32"/>
+  <reg name="r0" bitsize="32" type="uint32"/>
+  <reg name="r1" bitsize="32" type="uint32"/>
+  <reg name="r2" bitsize="32" type="uint32"/>
+  <reg name="r3" bitsize="32" type="uint32"/>
+  <reg name="r4" bitsize="32" type="uint32"/>
+  <reg name="r5" bitsize="32" type="uint32"/>
+  <reg name="r6" bitsize="32" type="uint32"/>
+  <reg name="r7" bitsize="32" type="uint32"/>
+  <reg name="r8" bitsize="32" type="uint32"/>
+  <reg name="r9" bitsize="32" type="uint32"/>
+  <reg name="r10" bitsize="32" type="uint32"/>
+  <reg name="r11" bitsize="32" type="uint32"/>
+  <reg name="r12" bitsize="32" type="uint32"/>
+  <reg name="sp" bitsize="32" type="data_ptr"/>

   <reg name="lr" bitsize="32"/>
   <reg name="lr" bitsize="32"/>

-  <reg name="pc" bitsize="32"/>
+  <reg name="pc" bitsize="32" type="code_ptr"/>

 
   <!-- The CPSR is register 25, rather than register 16, because
        the FPA registers historically were placed between the PC
 
   <!-- The CPSR is register 25, rather than register 16, because
        the FPA registers historically were placed between the PC