+ else
+ {
+ if (xcr0_features)
+ {
+ switch (xcr0 & X86_XSTATE_ALL_MASK)
+ {
+ case X86_XSTATE_AVX512_MASK:
+ return tdesc_x32_avx512_linux;
+
+ case X86_XSTATE_MPX_MASK: /* No MPX on x32. */
+ case X86_XSTATE_AVX_MASK:
+ return tdesc_x32_avx_linux;
+
+ default:
+ return tdesc_x32_linux;
+ }
+ }
+ else
+ return tdesc_x32_linux;
+ }
+#endif
+ }
+ else
+ {
+ if (xcr0_features)
+ {
+ switch (xcr0 & X86_XSTATE_ALL_MASK)
+ {
+ case (X86_XSTATE_AVX512_MASK):
+ return tdesc_i386_avx512_linux;
+
+ case (X86_XSTATE_MPX_MASK):
+ return tdesc_i386_mpx_linux;
+
+ case (X86_XSTATE_AVX_MASK):
+ return tdesc_i386_avx_linux;
+
+ default:
+ return tdesc_i386_linux;
+ }
+ }
+ else
+ return tdesc_i386_linux;
+ }
+
+ gdb_assert_not_reached ("failed to return tdesc");
+}
+
+/* Callback for find_inferior. Stops iteration when a thread with a
+ given PID is found. */
+
+static int
+same_process_callback (struct inferior_list_entry *entry, void *data)
+{
+ int pid = *(int *) data;
+
+ return (ptid_get_pid (entry->id) == pid);
+}
+
+/* Callback for for_each_inferior. Calls the arch_setup routine for
+ each process. */
+
+static void
+x86_arch_setup_process_callback (struct inferior_list_entry *entry)
+{
+ int pid = ptid_get_pid (entry->id);
+
+ /* Look up any thread of this processes. */
+ current_thread
+ = (struct thread_info *) find_inferior (&all_threads,
+ same_process_callback, &pid);
+
+ the_low_target.arch_setup ();
+}
+
+/* Update all the target description of all processes; a new GDB
+ connected, and it may or not support xml target descriptions. */
+
+static void
+x86_linux_update_xmltarget (void)
+{
+ struct thread_info *saved_thread = current_thread;
+
+ /* Before changing the register cache's internal layout, flush the
+ contents of the current valid caches back to the threads, and
+ release the current regcache objects. */
+ regcache_release ();
+
+ for_each_inferior (&all_processes, x86_arch_setup_process_callback);
+
+ current_thread = saved_thread;
+}
+
+/* Process qSupported query, "xmlRegisters=". Update the buffer size for
+ PTRACE_GETREGSET. */
+
+static void
+x86_linux_process_qsupported (char **features, int count)
+{
+ int i;
+
+ /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
+ with "i386" in qSupported query, it supports x86 XML target
+ descriptions. */
+ use_xml = 0;
+ for (i = 0; i < count; i++)
+ {
+ const char *feature = features[i];
+
+ if (startswith (feature, "xmlRegisters="))
+ {
+ char *copy = xstrdup (feature + 13);
+ char *p;
+
+ for (p = strtok (copy, ","); p != NULL; p = strtok (NULL, ","))
+ {
+ if (strcmp (p, "i386") == 0)
+ {
+ use_xml = 1;
+ break;
+ }
+ }
+
+ free (copy);
+ }
+ }
+ x86_linux_update_xmltarget ();
+}
+
+/* Common for x86/x86-64. */
+
+static struct regsets_info x86_regsets_info =
+ {
+ x86_regsets, /* regsets */
+ 0, /* num_regsets */
+ NULL, /* disabled_regsets */
+ };
+
+#ifdef __x86_64__
+static struct regs_info amd64_linux_regs_info =
+ {
+ NULL, /* regset_bitmap */
+ NULL, /* usrregs_info */
+ &x86_regsets_info
+ };
+#endif
+static struct usrregs_info i386_linux_usrregs_info =
+ {
+ I386_NUM_REGS,
+ i386_regmap,
+ };
+
+static struct regs_info i386_linux_regs_info =
+ {
+ NULL, /* regset_bitmap */
+ &i386_linux_usrregs_info,
+ &x86_regsets_info
+ };
+
+const struct regs_info *
+x86_linux_regs_info (void)
+{
+#ifdef __x86_64__
+ if (is_64bit_tdesc ())
+ return &amd64_linux_regs_info;
+ else
+#endif
+ return &i386_linux_regs_info;
+}
+
+/* Initialize the target description for the architecture of the
+ inferior. */
+
+static void
+x86_arch_setup (void)
+{
+ current_process ()->tdesc = x86_linux_read_description ();
+}
+
+/* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
+ code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
+
+static void
+x86_get_syscall_trapinfo (struct regcache *regcache, int *sysno, int *sysret)
+{
+ int use_64bit = register_size (regcache->tdesc, 0) == 8;
+
+ if (use_64bit)
+ {
+ long l_sysno;
+ long l_sysret;
+
+ collect_register_by_name (regcache, "orig_rax", &l_sysno);
+ collect_register_by_name (regcache, "rax", &l_sysret);
+ *sysno = (int) l_sysno;
+ *sysret = (int) l_sysret;
+ }
+ else
+ {
+ collect_register_by_name (regcache, "orig_eax", sysno);
+ collect_register_by_name (regcache, "eax", sysret);
+ }
+}
+
+static int
+x86_supports_tracepoints (void)
+{
+ return 1;
+}
+
+static void
+append_insns (CORE_ADDR *to, size_t len, const unsigned char *buf)
+{
+ write_inferior_memory (*to, buf, len);
+ *to += len;
+}
+
+static int
+push_opcode (unsigned char *buf, char *op)
+{
+ unsigned char *buf_org = buf;
+
+ while (1)
+ {
+ char *endptr;
+ unsigned long ul = strtoul (op, &endptr, 16);
+
+ if (endptr == op)
+ break;
+
+ *buf++ = ul;
+ op = endptr;
+ }
+
+ return buf - buf_org;
+}
+
+#ifdef __x86_64__
+
+/* Build a jump pad that saves registers and calls a collection
+ function. Writes a jump instruction to the jump pad to
+ JJUMPAD_INSN. The caller is responsible to write it in at the
+ tracepoint address. */
+
+static int
+amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
+ CORE_ADDR collector,
+ CORE_ADDR lockaddr,
+ ULONGEST orig_size,
+ CORE_ADDR *jump_entry,
+ CORE_ADDR *trampoline,
+ ULONGEST *trampoline_size,
+ unsigned char *jjump_pad_insn,
+ ULONGEST *jjump_pad_insn_size,
+ CORE_ADDR *adjusted_insn_addr,
+ CORE_ADDR *adjusted_insn_addr_end,
+ char *err)
+{
+ unsigned char buf[40];
+ int i, offset;
+ int64_t loffset;
+
+ CORE_ADDR buildaddr = *jump_entry;
+
+ /* Build the jump pad. */
+
+ /* First, do tracepoint data collection. Save registers. */
+ i = 0;
+ /* Need to ensure stack pointer saved first. */
+ buf[i++] = 0x54; /* push %rsp */
+ buf[i++] = 0x55; /* push %rbp */
+ buf[i++] = 0x57; /* push %rdi */
+ buf[i++] = 0x56; /* push %rsi */
+ buf[i++] = 0x52; /* push %rdx */
+ buf[i++] = 0x51; /* push %rcx */
+ buf[i++] = 0x53; /* push %rbx */
+ buf[i++] = 0x50; /* push %rax */
+ buf[i++] = 0x41; buf[i++] = 0x57; /* push %r15 */
+ buf[i++] = 0x41; buf[i++] = 0x56; /* push %r14 */
+ buf[i++] = 0x41; buf[i++] = 0x55; /* push %r13 */
+ buf[i++] = 0x41; buf[i++] = 0x54; /* push %r12 */
+ buf[i++] = 0x41; buf[i++] = 0x53; /* push %r11 */
+ buf[i++] = 0x41; buf[i++] = 0x52; /* push %r10 */
+ buf[i++] = 0x41; buf[i++] = 0x51; /* push %r9 */
+ buf[i++] = 0x41; buf[i++] = 0x50; /* push %r8 */
+ buf[i++] = 0x9c; /* pushfq */
+ buf[i++] = 0x48; /* movl <addr>,%rdi */
+ buf[i++] = 0xbf;
+ *((unsigned long *)(buf + i)) = (unsigned long) tpaddr;
+ i += sizeof (unsigned long);
+ buf[i++] = 0x57; /* push %rdi */
+ append_insns (&buildaddr, i, buf);
+
+ /* Stack space for the collecting_t object. */
+ i = 0;
+ i += push_opcode (&buf[i], "48 83 ec 18"); /* sub $0x18,%rsp */
+ i += push_opcode (&buf[i], "48 b8"); /* mov <tpoint>,%rax */
+ memcpy (buf + i, &tpoint, 8);
+ i += 8;
+ i += push_opcode (&buf[i], "48 89 04 24"); /* mov %rax,(%rsp) */
+ i += push_opcode (&buf[i],
+ "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
+ i += push_opcode (&buf[i], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
+ append_insns (&buildaddr, i, buf);
+
+ /* spin-lock. */
+ i = 0;
+ i += push_opcode (&buf[i], "48 be"); /* movl <lockaddr>,%rsi */
+ memcpy (&buf[i], (void *) &lockaddr, 8);
+ i += 8;
+ i += push_opcode (&buf[i], "48 89 e1"); /* mov %rsp,%rcx */
+ i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
+ i += push_opcode (&buf[i], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
+ i += push_opcode (&buf[i], "48 85 c0"); /* test %rax,%rax */
+ i += push_opcode (&buf[i], "75 f4"); /* jne <again> */
+ append_insns (&buildaddr, i, buf);
+
+ /* Set up the gdb_collect call. */
+ /* At this point, (stack pointer + 0x18) is the base of our saved
+ register block. */
+
+ i = 0;
+ i += push_opcode (&buf[i], "48 89 e6"); /* mov %rsp,%rsi */
+ i += push_opcode (&buf[i], "48 83 c6 18"); /* add $0x18,%rsi */
+
+ /* tpoint address may be 64-bit wide. */
+ i += push_opcode (&buf[i], "48 bf"); /* movl <addr>,%rdi */
+ memcpy (buf + i, &tpoint, 8);
+ i += 8;
+ append_insns (&buildaddr, i, buf);
+
+ /* The collector function being in the shared library, may be
+ >31-bits away off the jump pad. */
+ i = 0;
+ i += push_opcode (&buf[i], "48 b8"); /* mov $collector,%rax */
+ memcpy (buf + i, &collector, 8);
+ i += 8;
+ i += push_opcode (&buf[i], "ff d0"); /* callq *%rax */
+ append_insns (&buildaddr, i, buf);
+
+ /* Clear the spin-lock. */
+ i = 0;
+ i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
+ i += push_opcode (&buf[i], "48 a3"); /* mov %rax, lockaddr */
+ memcpy (buf + i, &lockaddr, 8);
+ i += 8;
+ append_insns (&buildaddr, i, buf);
+
+ /* Remove stack that had been used for the collect_t object. */
+ i = 0;
+ i += push_opcode (&buf[i], "48 83 c4 18"); /* add $0x18,%rsp */
+ append_insns (&buildaddr, i, buf);
+
+ /* Restore register state. */
+ i = 0;
+ buf[i++] = 0x48; /* add $0x8,%rsp */
+ buf[i++] = 0x83;
+ buf[i++] = 0xc4;
+ buf[i++] = 0x08;
+ buf[i++] = 0x9d; /* popfq */
+ buf[i++] = 0x41; buf[i++] = 0x58; /* pop %r8 */
+ buf[i++] = 0x41; buf[i++] = 0x59; /* pop %r9 */
+ buf[i++] = 0x41; buf[i++] = 0x5a; /* pop %r10 */
+ buf[i++] = 0x41; buf[i++] = 0x5b; /* pop %r11 */
+ buf[i++] = 0x41; buf[i++] = 0x5c; /* pop %r12 */
+ buf[i++] = 0x41; buf[i++] = 0x5d; /* pop %r13 */
+ buf[i++] = 0x41; buf[i++] = 0x5e; /* pop %r14 */
+ buf[i++] = 0x41; buf[i++] = 0x5f; /* pop %r15 */
+ buf[i++] = 0x58; /* pop %rax */
+ buf[i++] = 0x5b; /* pop %rbx */
+ buf[i++] = 0x59; /* pop %rcx */
+ buf[i++] = 0x5a; /* pop %rdx */
+ buf[i++] = 0x5e; /* pop %rsi */
+ buf[i++] = 0x5f; /* pop %rdi */
+ buf[i++] = 0x5d; /* pop %rbp */
+ buf[i++] = 0x5c; /* pop %rsp */
+ append_insns (&buildaddr, i, buf);
+
+ /* Now, adjust the original instruction to execute in the jump
+ pad. */
+ *adjusted_insn_addr = buildaddr;
+ relocate_instruction (&buildaddr, tpaddr);
+ *adjusted_insn_addr_end = buildaddr;
+
+ /* Finally, write a jump back to the program. */
+
+ loffset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn));
+ if (loffset > INT_MAX || loffset < INT_MIN)
+ {
+ sprintf (err,
+ "E.Jump back from jump pad too far from tracepoint "
+ "(offset 0x%" PRIx64 " > int32).", loffset);
+ return 1;
+ }
+
+ offset = (int) loffset;
+ memcpy (buf, jump_insn, sizeof (jump_insn));
+ memcpy (buf + 1, &offset, 4);
+ append_insns (&buildaddr, sizeof (jump_insn), buf);
+
+ /* The jump pad is now built. Wire in a jump to our jump pad. This
+ is always done last (by our caller actually), so that we can
+ install fast tracepoints with threads running. This relies on
+ the agent's atomic write support. */
+ loffset = *jump_entry - (tpaddr + sizeof (jump_insn));
+ if (loffset > INT_MAX || loffset < INT_MIN)
+ {
+ sprintf (err,
+ "E.Jump pad too far from tracepoint "
+ "(offset 0x%" PRIx64 " > int32).", loffset);
+ return 1;
+ }
+
+ offset = (int) loffset;
+
+ memcpy (buf, jump_insn, sizeof (jump_insn));
+ memcpy (buf + 1, &offset, 4);
+ memcpy (jjump_pad_insn, buf, sizeof (jump_insn));
+ *jjump_pad_insn_size = sizeof (jump_insn);
+
+ /* Return the end address of our pad. */
+ *jump_entry = buildaddr;
+
+ return 0;
+}
+
+#endif /* __x86_64__ */
+
+/* Build a jump pad that saves registers and calls a collection
+ function. Writes a jump instruction to the jump pad to
+ JJUMPAD_INSN. The caller is responsible to write it in at the
+ tracepoint address. */
+
+static int
+i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
+ CORE_ADDR collector,
+ CORE_ADDR lockaddr,
+ ULONGEST orig_size,
+ CORE_ADDR *jump_entry,
+ CORE_ADDR *trampoline,
+ ULONGEST *trampoline_size,
+ unsigned char *jjump_pad_insn,
+ ULONGEST *jjump_pad_insn_size,
+ CORE_ADDR *adjusted_insn_addr,
+ CORE_ADDR *adjusted_insn_addr_end,
+ char *err)
+{
+ unsigned char buf[0x100];
+ int i, offset;
+ CORE_ADDR buildaddr = *jump_entry;
+
+ /* Build the jump pad. */
+
+ /* First, do tracepoint data collection. Save registers. */
+ i = 0;
+ buf[i++] = 0x60; /* pushad */
+ buf[i++] = 0x68; /* push tpaddr aka $pc */
+ *((int *)(buf + i)) = (int) tpaddr;
+ i += 4;
+ buf[i++] = 0x9c; /* pushf */
+ buf[i++] = 0x1e; /* push %ds */
+ buf[i++] = 0x06; /* push %es */
+ buf[i++] = 0x0f; /* push %fs */
+ buf[i++] = 0xa0;
+ buf[i++] = 0x0f; /* push %gs */
+ buf[i++] = 0xa8;
+ buf[i++] = 0x16; /* push %ss */
+ buf[i++] = 0x0e; /* push %cs */
+ append_insns (&buildaddr, i, buf);
+
+ /* Stack space for the collecting_t object. */
+ i = 0;
+ i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */
+
+ /* Build the object. */
+ i += push_opcode (&buf[i], "b8"); /* mov <tpoint>,%eax */
+ memcpy (buf + i, &tpoint, 4);
+ i += 4;
+ i += push_opcode (&buf[i], "89 04 24"); /* mov %eax,(%esp) */
+
+ i += push_opcode (&buf[i], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
+ i += push_opcode (&buf[i], "89 44 24 04"); /* mov %eax,0x4(%esp) */
+ append_insns (&buildaddr, i, buf);
+
+ /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
+ If we cared for it, this could be using xchg alternatively. */
+
+ i = 0;
+ i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
+ i += push_opcode (&buf[i], "f0 0f b1 25"); /* lock cmpxchg
+ %esp,<lockaddr> */
+ memcpy (&buf[i], (void *) &lockaddr, 4);
+ i += 4;
+ i += push_opcode (&buf[i], "85 c0"); /* test %eax,%eax */
+ i += push_opcode (&buf[i], "75 f2"); /* jne <again> */
+ append_insns (&buildaddr, i, buf);
+
+
+ /* Set up arguments to the gdb_collect call. */
+ i = 0;
+ i += push_opcode (&buf[i], "89 e0"); /* mov %esp,%eax */
+ i += push_opcode (&buf[i], "83 c0 08"); /* add $0x08,%eax */
+ i += push_opcode (&buf[i], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
+ append_insns (&buildaddr, i, buf);
+
+ i = 0;
+ i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */
+ append_insns (&buildaddr, i, buf);
+
+ i = 0;
+ i += push_opcode (&buf[i], "c7 04 24"); /* movl <addr>,(%esp) */
+ memcpy (&buf[i], (void *) &tpoint, 4);
+ i += 4;
+ append_insns (&buildaddr, i, buf);
+
+ buf[0] = 0xe8; /* call <reladdr> */
+ offset = collector - (buildaddr + sizeof (jump_insn));
+ memcpy (buf + 1, &offset, 4);
+ append_insns (&buildaddr, 5, buf);
+ /* Clean up after the call. */
+ buf[0] = 0x83; /* add $0x8,%esp */
+ buf[1] = 0xc4;
+ buf[2] = 0x08;
+ append_insns (&buildaddr, 3, buf);
+
+
+ /* Clear the spin-lock. This would need the LOCK prefix on older
+ broken archs. */
+ i = 0;
+ i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
+ i += push_opcode (&buf[i], "a3"); /* mov %eax, lockaddr */
+ memcpy (buf + i, &lockaddr, 4);
+ i += 4;
+ append_insns (&buildaddr, i, buf);
+
+
+ /* Remove stack that had been used for the collect_t object. */
+ i = 0;
+ i += push_opcode (&buf[i], "83 c4 08"); /* add $0x08,%esp */
+ append_insns (&buildaddr, i, buf);
+
+ i = 0;
+ buf[i++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
+ buf[i++] = 0xc4;
+ buf[i++] = 0x04;
+ buf[i++] = 0x17; /* pop %ss */
+ buf[i++] = 0x0f; /* pop %gs */
+ buf[i++] = 0xa9;
+ buf[i++] = 0x0f; /* pop %fs */
+ buf[i++] = 0xa1;
+ buf[i++] = 0x07; /* pop %es */
+ buf[i++] = 0x1f; /* pop %ds */
+ buf[i++] = 0x9d; /* popf */
+ buf[i++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
+ buf[i++] = 0xc4;
+ buf[i++] = 0x04;
+ buf[i++] = 0x61; /* popad */
+ append_insns (&buildaddr, i, buf);
+
+ /* Now, adjust the original instruction to execute in the jump
+ pad. */
+ *adjusted_insn_addr = buildaddr;
+ relocate_instruction (&buildaddr, tpaddr);
+ *adjusted_insn_addr_end = buildaddr;
+
+ /* Write the jump back to the program. */
+ offset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn));
+ memcpy (buf, jump_insn, sizeof (jump_insn));
+ memcpy (buf + 1, &offset, 4);
+ append_insns (&buildaddr, sizeof (jump_insn), buf);
+
+ /* The jump pad is now built. Wire in a jump to our jump pad. This
+ is always done last (by our caller actually), so that we can
+ install fast tracepoints with threads running. This relies on
+ the agent's atomic write support. */
+ if (orig_size == 4)
+ {
+ /* Create a trampoline. */
+ *trampoline_size = sizeof (jump_insn);
+ if (!claim_trampoline_space (*trampoline_size, trampoline))
+ {
+ /* No trampoline space available. */
+ strcpy (err,
+ "E.Cannot allocate trampoline space needed for fast "
+ "tracepoints on 4-byte instructions.");
+ return 1;
+ }
+
+ offset = *jump_entry - (*trampoline + sizeof (jump_insn));
+ memcpy (buf, jump_insn, sizeof (jump_insn));
+ memcpy (buf + 1, &offset, 4);
+ write_inferior_memory (*trampoline, buf, sizeof (jump_insn));
+
+ /* Use a 16-bit relative jump instruction to jump to the trampoline. */
+ offset = (*trampoline - (tpaddr + sizeof (small_jump_insn))) & 0xffff;
+ memcpy (buf, small_jump_insn, sizeof (small_jump_insn));
+ memcpy (buf + 2, &offset, 2);
+ memcpy (jjump_pad_insn, buf, sizeof (small_jump_insn));
+ *jjump_pad_insn_size = sizeof (small_jump_insn);
+ }
+ else
+ {
+ /* Else use a 32-bit relative jump instruction. */
+ offset = *jump_entry - (tpaddr + sizeof (jump_insn));
+ memcpy (buf, jump_insn, sizeof (jump_insn));
+ memcpy (buf + 1, &offset, 4);
+ memcpy (jjump_pad_insn, buf, sizeof (jump_insn));
+ *jjump_pad_insn_size = sizeof (jump_insn);
+ }
+
+ /* Return the end address of our pad. */
+ *jump_entry = buildaddr;
+
+ return 0;
+}
+
+static int
+x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
+ CORE_ADDR collector,
+ CORE_ADDR lockaddr,
+ ULONGEST orig_size,
+ CORE_ADDR *jump_entry,
+ CORE_ADDR *trampoline,
+ ULONGEST *trampoline_size,
+ unsigned char *jjump_pad_insn,
+ ULONGEST *jjump_pad_insn_size,
+ CORE_ADDR *adjusted_insn_addr,
+ CORE_ADDR *adjusted_insn_addr_end,
+ char *err)
+{
+#ifdef __x86_64__
+ if (is_64bit_tdesc ())
+ return amd64_install_fast_tracepoint_jump_pad (tpoint, tpaddr,
+ collector, lockaddr,
+ orig_size, jump_entry,
+ trampoline, trampoline_size,
+ jjump_pad_insn,
+ jjump_pad_insn_size,
+ adjusted_insn_addr,
+ adjusted_insn_addr_end,
+ err);
+#endif
+
+ return i386_install_fast_tracepoint_jump_pad (tpoint, tpaddr,
+ collector, lockaddr,
+ orig_size, jump_entry,
+ trampoline, trampoline_size,
+ jjump_pad_insn,
+ jjump_pad_insn_size,
+ adjusted_insn_addr,
+ adjusted_insn_addr_end,
+ err);
+}
+
+/* Return the minimum instruction length for fast tracepoints on x86/x86-64
+ architectures. */
+
+static int
+x86_get_min_fast_tracepoint_insn_len (void)
+{
+ static int warned_about_fast_tracepoints = 0;
+
+#ifdef __x86_64__
+ /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
+ used for fast tracepoints. */
+ if (is_64bit_tdesc ())
+ return 5;
+#endif
+
+ if (agent_loaded_p ())
+ {
+ char errbuf[IPA_BUFSIZ];
+
+ errbuf[0] = '\0';
+
+ /* On x86, if trampolines are available, then 4-byte jump instructions
+ with a 2-byte offset may be used, otherwise 5-byte jump instructions
+ with a 4-byte offset are used instead. */
+ if (have_fast_tracepoint_trampoline_buffer (errbuf))
+ return 4;
+ else
+ {
+ /* GDB has no channel to explain to user why a shorter fast
+ tracepoint is not possible, but at least make GDBserver
+ mention that something has gone awry. */
+ if (!warned_about_fast_tracepoints)
+ {
+ warning ("4-byte fast tracepoints not available; %s\n", errbuf);
+ warned_about_fast_tracepoints = 1;
+ }
+ return 5;
+ }
+ }
+ else
+ {
+ /* Indicate that the minimum length is currently unknown since the IPA
+ has not loaded yet. */
+ return 0;
+ }
+}
+
+static void
+add_insns (unsigned char *start, int len)
+{
+ CORE_ADDR buildaddr = current_insn_ptr;
+
+ if (debug_threads)
+ debug_printf ("Adding %d bytes of insn at %s\n",
+ len, paddress (buildaddr));
+
+ append_insns (&buildaddr, len, start);
+ current_insn_ptr = buildaddr;
+}
+
+/* Our general strategy for emitting code is to avoid specifying raw
+ bytes whenever possible, and instead copy a block of inline asm
+ that is embedded in the function. This is a little messy, because
+ we need to keep the compiler from discarding what looks like dead
+ code, plus suppress various warnings. */
+
+#define EMIT_ASM(NAME, INSNS) \
+ do \
+ { \
+ extern unsigned char start_ ## NAME, end_ ## NAME; \
+ add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
+ __asm__ ("jmp end_" #NAME "\n" \
+ "\t" "start_" #NAME ":" \
+ "\t" INSNS "\n" \
+ "\t" "end_" #NAME ":"); \
+ } while (0)
+
+#ifdef __x86_64__
+
+#define EMIT_ASM32(NAME,INSNS) \
+ do \
+ { \
+ extern unsigned char start_ ## NAME, end_ ## NAME; \
+ add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
+ __asm__ (".code32\n" \
+ "\t" "jmp end_" #NAME "\n" \
+ "\t" "start_" #NAME ":\n" \
+ "\t" INSNS "\n" \
+ "\t" "end_" #NAME ":\n" \
+ ".code64\n"); \
+ } while (0)
+
+#else
+
+#define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
+
+#endif
+
+#ifdef __x86_64__
+
+static void
+amd64_emit_prologue (void)
+{
+ EMIT_ASM (amd64_prologue,
+ "pushq %rbp\n\t"
+ "movq %rsp,%rbp\n\t"
+ "sub $0x20,%rsp\n\t"
+ "movq %rdi,-8(%rbp)\n\t"
+ "movq %rsi,-16(%rbp)");
+}
+
+
+static void
+amd64_emit_epilogue (void)
+{
+ EMIT_ASM (amd64_epilogue,
+ "movq -16(%rbp),%rdi\n\t"
+ "movq %rax,(%rdi)\n\t"
+ "xor %rax,%rax\n\t"
+ "leave\n\t"
+ "ret");
+}
+
+static void
+amd64_emit_add (void)
+{
+ EMIT_ASM (amd64_add,
+ "add (%rsp),%rax\n\t"
+ "lea 0x8(%rsp),%rsp");
+}
+
+static void
+amd64_emit_sub (void)
+{
+ EMIT_ASM (amd64_sub,
+ "sub %rax,(%rsp)\n\t"
+ "pop %rax");
+}
+
+static void
+amd64_emit_mul (void)
+{
+ emit_error = 1;
+}
+
+static void
+amd64_emit_lsh (void)
+{
+ emit_error = 1;
+}
+
+static void
+amd64_emit_rsh_signed (void)
+{
+ emit_error = 1;
+}
+
+static void
+amd64_emit_rsh_unsigned (void)
+{
+ emit_error = 1;
+}
+
+static void
+amd64_emit_ext (int arg)
+{
+ switch (arg)
+ {
+ case 8:
+ EMIT_ASM (amd64_ext_8,
+ "cbtw\n\t"
+ "cwtl\n\t"
+ "cltq");
+ break;
+ case 16:
+ EMIT_ASM (amd64_ext_16,
+ "cwtl\n\t"
+ "cltq");
+ break;
+ case 32:
+ EMIT_ASM (amd64_ext_32,
+ "cltq");
+ break;
+ default:
+ emit_error = 1;
+ }
+}
+
+static void
+amd64_emit_log_not (void)
+{
+ EMIT_ASM (amd64_log_not,
+ "test %rax,%rax\n\t"
+ "sete %cl\n\t"
+ "movzbq %cl,%rax");
+}
+
+static void
+amd64_emit_bit_and (void)
+{
+ EMIT_ASM (amd64_and,
+ "and (%rsp),%rax\n\t"
+ "lea 0x8(%rsp),%rsp");
+}
+
+static void
+amd64_emit_bit_or (void)
+{
+ EMIT_ASM (amd64_or,
+ "or (%rsp),%rax\n\t"
+ "lea 0x8(%rsp),%rsp");
+}
+
+static void
+amd64_emit_bit_xor (void)
+{
+ EMIT_ASM (amd64_xor,
+ "xor (%rsp),%rax\n\t"
+ "lea 0x8(%rsp),%rsp");
+}
+
+static void
+amd64_emit_bit_not (void)
+{
+ EMIT_ASM (amd64_bit_not,
+ "xorq $0xffffffffffffffff,%rax");
+}
+
+static void
+amd64_emit_equal (void)
+{
+ EMIT_ASM (amd64_equal,
+ "cmp %rax,(%rsp)\n\t"
+ "je .Lamd64_equal_true\n\t"
+ "xor %rax,%rax\n\t"
+ "jmp .Lamd64_equal_end\n\t"
+ ".Lamd64_equal_true:\n\t"
+ "mov $0x1,%rax\n\t"
+ ".Lamd64_equal_end:\n\t"
+ "lea 0x8(%rsp),%rsp");
+}
+
+static void
+amd64_emit_less_signed (void)
+{
+ EMIT_ASM (amd64_less_signed,
+ "cmp %rax,(%rsp)\n\t"
+ "jl .Lamd64_less_signed_true\n\t"
+ "xor %rax,%rax\n\t"
+ "jmp .Lamd64_less_signed_end\n\t"
+ ".Lamd64_less_signed_true:\n\t"
+ "mov $1,%rax\n\t"
+ ".Lamd64_less_signed_end:\n\t"
+ "lea 0x8(%rsp),%rsp");
+}
+
+static void
+amd64_emit_less_unsigned (void)
+{
+ EMIT_ASM (amd64_less_unsigned,
+ "cmp %rax,(%rsp)\n\t"
+ "jb .Lamd64_less_unsigned_true\n\t"
+ "xor %rax,%rax\n\t"
+ "jmp .Lamd64_less_unsigned_end\n\t"
+ ".Lamd64_less_unsigned_true:\n\t"
+ "mov $1,%rax\n\t"
+ ".Lamd64_less_unsigned_end:\n\t"
+ "lea 0x8(%rsp),%rsp");
+}
+
+static void
+amd64_emit_ref (int size)
+{
+ switch (size)
+ {
+ case 1:
+ EMIT_ASM (amd64_ref1,
+ "movb (%rax),%al");
+ break;
+ case 2:
+ EMIT_ASM (amd64_ref2,
+ "movw (%rax),%ax");
+ break;
+ case 4:
+ EMIT_ASM (amd64_ref4,
+ "movl (%rax),%eax");
+ break;
+ case 8:
+ EMIT_ASM (amd64_ref8,
+ "movq (%rax),%rax");
+ break;
+ }
+}
+
+static void
+amd64_emit_if_goto (int *offset_p, int *size_p)
+{
+ EMIT_ASM (amd64_if_goto,
+ "mov %rax,%rcx\n\t"
+ "pop %rax\n\t"
+ "cmp $0,%rcx\n\t"
+ ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
+ if (offset_p)
+ *offset_p = 10;
+ if (size_p)
+ *size_p = 4;
+}
+
+static void
+amd64_emit_goto (int *offset_p, int *size_p)
+{
+ EMIT_ASM (amd64_goto,
+ ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
+ if (offset_p)
+ *offset_p = 1;
+ if (size_p)
+ *size_p = 4;
+}
+
+static void
+amd64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
+{
+ int diff = (to - (from + size));
+ unsigned char buf[sizeof (int)];
+
+ if (size != 4)
+ {
+ emit_error = 1;
+ return;
+ }
+
+ memcpy (buf, &diff, sizeof (int));
+ write_inferior_memory (from, buf, sizeof (int));
+}
+
+static void
+amd64_emit_const (LONGEST num)
+{
+ unsigned char buf[16];
+ int i;
+ CORE_ADDR buildaddr = current_insn_ptr;
+
+ i = 0;
+ buf[i++] = 0x48; buf[i++] = 0xb8; /* mov $<n>,%rax */
+ memcpy (&buf[i], &num, sizeof (num));
+ i += 8;
+ append_insns (&buildaddr, i, buf);
+ current_insn_ptr = buildaddr;
+}
+
+static void
+amd64_emit_call (CORE_ADDR fn)
+{
+ unsigned char buf[16];
+ int i;
+ CORE_ADDR buildaddr;
+ LONGEST offset64;
+
+ /* The destination function being in the shared library, may be
+ >31-bits away off the compiled code pad. */
+
+ buildaddr = current_insn_ptr;
+
+ offset64 = fn - (buildaddr + 1 /* call op */ + 4 /* 32-bit offset */);
+
+ i = 0;
+
+ if (offset64 > INT_MAX || offset64 < INT_MIN)
+ {
+ /* Offset is too large for a call. Use callq, but that requires
+ a register, so avoid it if possible. Use r10, since it is
+ call-clobbered, we don't have to push/pop it. */
+ buf[i++] = 0x48; /* mov $fn,%r10 */
+ buf[i++] = 0xba;
+ memcpy (buf + i, &fn, 8);
+ i += 8;
+ buf[i++] = 0xff; /* callq *%r10 */
+ buf[i++] = 0xd2;
+ }
+ else
+ {
+ int offset32 = offset64; /* we know we can't overflow here. */
+ memcpy (buf + i, &offset32, 4);
+ i += 4;
+ }
+
+ append_insns (&buildaddr, i, buf);
+ current_insn_ptr = buildaddr;
+}
+
+static void
+amd64_emit_reg (int reg)
+{
+ unsigned char buf[16];
+ int i;
+ CORE_ADDR buildaddr;
+
+ /* Assume raw_regs is still in %rdi. */
+ buildaddr = current_insn_ptr;
+ i = 0;
+ buf[i++] = 0xbe; /* mov $<n>,%esi */
+ memcpy (&buf[i], ®, sizeof (reg));
+ i += 4;
+ append_insns (&buildaddr, i, buf);
+ current_insn_ptr = buildaddr;
+ amd64_emit_call (get_raw_reg_func_addr ());
+}
+
+static void
+amd64_emit_pop (void)
+{
+ EMIT_ASM (amd64_pop,
+ "pop %rax");
+}
+
+static void
+amd64_emit_stack_flush (void)
+{
+ EMIT_ASM (amd64_stack_flush,
+ "push %rax");
+}
+
+static void
+amd64_emit_zero_ext (int arg)
+{
+ switch (arg)
+ {
+ case 8:
+ EMIT_ASM (amd64_zero_ext_8,
+ "and $0xff,%rax");
+ break;
+ case 16:
+ EMIT_ASM (amd64_zero_ext_16,
+ "and $0xffff,%rax");
+ break;
+ case 32:
+ EMIT_ASM (amd64_zero_ext_32,
+ "mov $0xffffffff,%rcx\n\t"
+ "and %rcx,%rax");
+ break;
+ default:
+ emit_error = 1;
+ }
+}