-#ifdef I386_USE_GENERIC_WATCHPOINTS
-
-/* Support for 8-byte wide hw watchpoints. */
-#ifndef TARGET_HAS_DR_LEN_8
-#define TARGET_HAS_DR_LEN_8 0
-#endif
-
-/* Debug registers' indices. */
-#define DR_NADDR 4 /* The number of debug address registers. */
-#define DR_STATUS 6 /* Index of debug status register (DR6). */
-#define DR_CONTROL 7 /* Index of debug control register (DR7). */
-
-/* DR7 Debug Control register fields. */
-
-/* How many bits to skip in DR7 to get to R/W and LEN fields. */
-#define DR_CONTROL_SHIFT 16
-/* How many bits in DR7 per R/W and LEN field for each watchpoint. */
-#define DR_CONTROL_SIZE 4
-
-/* Watchpoint/breakpoint read/write fields in DR7. */
-#define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
-#define DR_RW_WRITE (0x1) /* Break on data writes. */
-#define DR_RW_READ (0x3) /* Break on data reads or writes. */
-
-/* This is here for completeness. No platform supports this
- functionality yet (as of March 2001). Note that the DE flag in the
- CR4 register needs to be set to support this. */
-#ifndef DR_RW_IORW
-#define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
-#endif
-
-/* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
- is so we could OR this with the read/write field defined above. */
-#define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
-#define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
-#define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
-#define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
-
-/* Local and Global Enable flags in DR7.
-
- When the Local Enable flag is set, the breakpoint/watchpoint is
- enabled only for the current task; the processor automatically
- clears this flag on every task switch. When the Global Enable flag
- is set, the breakpoint/watchpoint is enabled for all tasks; the
- processor never clears this flag.
-
- Currently, all watchpoint are locally enabled. If you need to
- enable them globally, read the comment which pertains to this in
- i386_insert_aligned_watchpoint below. */
-#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
-#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
-#define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
-
-/* Local and global exact breakpoint enable flags (a.k.a. slowdown
- flags). These are only required on i386, to allow detection of the
- exact instruction which caused a watchpoint to break; i486 and
- later processors do that automatically. We set these flags for
- backwards compatibility. */
-#define DR_LOCAL_SLOWDOWN (0x100)
-#define DR_GLOBAL_SLOWDOWN (0x200)
-
-/* Fields reserved by Intel. This includes the GD (General Detect
- Enable) flag, which causes a debug exception to be generated when a
- MOV instruction accesses one of the debug registers.
-
- FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
-#define DR_CONTROL_RESERVED (0xFC00)
-
-/* Auxiliary helper macros. */
-
-/* A value that masks all fields in DR7 that are reserved by Intel. */
-#define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
-
-/* The I'th debug register is vacant if its Local and Global Enable
- bits are reset in the Debug Control register. */
-#define I386_DR_VACANT(i) \
- ((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
-
-/* Locally enable the break/watchpoint in the I'th debug register. */
-#define I386_DR_LOCAL_ENABLE(i) \
- dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
-
-/* Globally enable the break/watchpoint in the I'th debug register. */
-#define I386_DR_GLOBAL_ENABLE(i) \
- dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
-
-/* Disable the break/watchpoint in the I'th debug register. */
-#define I386_DR_DISABLE(i) \
- dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i)))
-
-/* Set in DR7 the RW and LEN fields for the I'th debug register. */
-#define I386_DR_SET_RW_LEN(i,rwlen) \
- do { \
- dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \
- dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \
- } while (0)
-
-/* Get from DR7 the RW and LEN fields for the I'th debug register. */
-#define I386_DR_GET_RW_LEN(i) \
- ((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
-
-/* Did the watchpoint whose address is in the I'th register break? */
-#define I386_DR_WATCH_HIT(i) (dr_status_mirror & (1 << (i)))
-
-/* A macro to loop over all debug registers. */
-#define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
-
-/* Mirror the inferior's DRi registers. We keep the status and
- control registers separated because they don't hold addresses. */
-static CORE_ADDR dr_mirror[DR_NADDR];
-static unsigned dr_status_mirror, dr_control_mirror;
-
-/* Reference counts for each debug register. */
-static int dr_ref_count[DR_NADDR];