+ errno = 0;
+ slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p.get ());
+ if (slot < 0)
+ perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
+
+ /* Everything went fine, so we have to register this *point. */
+ t = hwdebug_find_thread_points_by_tid (tid, 1);
+ gdb_assert (t != NULL);
+ hw_breaks = t->hw_breaks;
+
+ /* Find a free element in the hw_breaks vector. */
+ for (i = 0; i < max_slots_number; i++)
+ if (hw_breaks[i].hw_break == NULL)
+ {
+ hw_breaks[i].slot = slot;
+ hw_breaks[i].hw_break = p.release ();
+ break;
+ }
+
+ gdb_assert (i != max_slots_number);
+}
+
+/* This function is a generic wrapper that is responsible for removing a
+ *point (i.e., calling `ptrace' in order to issue the request to the
+ kernel), and unregistering it internally at GDB. */
+static void
+hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid)
+{
+ int i;
+ struct hw_break_tuple *hw_breaks;
+ struct thread_points *t;
+
+ t = hwdebug_find_thread_points_by_tid (tid, 0);
+ gdb_assert (t != NULL);
+ hw_breaks = t->hw_breaks;
+
+ for (i = 0; i < max_slots_number; i++)
+ if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b))
+ break;
+
+ gdb_assert (i != max_slots_number);
+
+ /* We have to ignore ENOENT errors because the kernel implements hardware
+ breakpoints/watchpoints as "one-shot", that is, they are automatically
+ deleted when hit. */
+ errno = 0;
+ if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0)
+ if (errno != ENOENT)
+ perror_with_name (_("Unexpected error deleting "
+ "breakpoint or watchpoint"));
+
+ xfree (hw_breaks[i].hw_break);
+ hw_breaks[i].hw_break = NULL;
+}
+
+/* Return the number of registers needed for a ranged breakpoint. */
+
+int
+ppc_linux_nat_target::ranged_break_num_registers ()
+{
+ return ((have_ptrace_hwdebug_interface ()
+ && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)?
+ 2 : -1);
+}
+
+/* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
+ success, 1 if hardware breakpoints are not supported or -1 for failure. */
+
+int
+ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
+{
+ struct lwp_info *lp;
+ struct ppc_hw_breakpoint p;
+
+ if (!have_ptrace_hwdebug_interface ())
+ return -1;
+
+ p.version = PPC_DEBUG_CURRENT_VERSION;
+ p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
+ p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+ p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address);
+ p.condition_value = 0;
+
+ if (bp_tgt->length)
+ {
+ p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
+
+ /* The breakpoint will trigger if the address of the instruction is
+ within the defined range, as follows: p.addr <= address < p.addr2. */
+ p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
+ }
+ else
+ {
+ p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
+ p.addr2 = 0;
+ }
+
+ ALL_LWPS (lp)
+ hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
+
+ return 0;
+}
+
+int
+ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
+{
+ struct lwp_info *lp;
+ struct ppc_hw_breakpoint p;
+
+ if (!have_ptrace_hwdebug_interface ())
+ return -1;
+
+ p.version = PPC_DEBUG_CURRENT_VERSION;
+ p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
+ p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+ p.addr = (uint64_t) bp_tgt->placed_address;
+ p.condition_value = 0;
+
+ if (bp_tgt->length)
+ {
+ p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
+
+ /* The breakpoint will trigger if the address of the instruction is within
+ the defined range, as follows: p.addr <= address < p.addr2. */
+ p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
+ }
+ else
+ {
+ p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
+ p.addr2 = 0;
+ }
+
+ ALL_LWPS (lp)
+ hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
+
+ return 0;
+}
+
+static int
+get_trigger_type (enum target_hw_bp_type type)
+{
+ int t;
+
+ if (type == hw_read)
+ t = PPC_BREAKPOINT_TRIGGER_READ;
+ else if (type == hw_write)
+ t = PPC_BREAKPOINT_TRIGGER_WRITE;
+ else
+ t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE;
+
+ return t;
+}
+
+/* Insert a new masked watchpoint at ADDR using the mask MASK.
+ RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
+ or hw_access for an access watchpoint. Returns 0 on success and throws
+ an error on failure. */
+
+int
+ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask,
+ target_hw_bp_type rw)
+{
+ struct lwp_info *lp;
+ struct ppc_hw_breakpoint p;
+
+ gdb_assert (have_ptrace_hwdebug_interface ());
+
+ p.version = PPC_DEBUG_CURRENT_VERSION;
+ p.trigger_type = get_trigger_type (rw);
+ p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
+ p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+ p.addr = addr;
+ p.addr2 = mask;
+ p.condition_value = 0;
+
+ ALL_LWPS (lp)
+ hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
+
+ return 0;
+}
+
+/* Remove a masked watchpoint at ADDR with the mask MASK.
+ RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
+ or hw_access for an access watchpoint. Returns 0 on success and throws
+ an error on failure. */
+
+int
+ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask,
+ target_hw_bp_type rw)
+{
+ struct lwp_info *lp;
+ struct ppc_hw_breakpoint p;
+
+ gdb_assert (have_ptrace_hwdebug_interface ());
+
+ p.version = PPC_DEBUG_CURRENT_VERSION;
+ p.trigger_type = get_trigger_type (rw);
+ p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
+ p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+ p.addr = addr;
+ p.addr2 = mask;
+ p.condition_value = 0;
+
+ ALL_LWPS (lp)
+ hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
+
+ return 0;
+}
+
+/* Check whether we have at least one free DVC register. */
+static int
+can_use_watchpoint_cond_accel (void)
+{
+ struct thread_points *p;
+ int tid = ptid_get_lwp (inferior_ptid);
+ int cnt = hwdebug_info.num_condition_regs, i;
+ CORE_ADDR tmp_value;
+
+ if (!have_ptrace_hwdebug_interface () || cnt == 0)
+ return 0;
+
+ p = hwdebug_find_thread_points_by_tid (tid, 0);
+
+ if (p)
+ {
+ for (i = 0; i < max_slots_number; i++)
+ if (p->hw_breaks[i].hw_break != NULL
+ && (p->hw_breaks[i].hw_break->condition_mode
+ != PPC_BREAKPOINT_CONDITION_NONE))
+ cnt--;
+
+ /* There are no available slots now. */
+ if (cnt <= 0)
+ return 0;
+ }
+
+ return 1;
+}
+
+/* Calculate the enable bits and the contents of the Data Value Compare
+ debug register present in BookE processors.
+
+ ADDR is the address to be watched, LEN is the length of watched data
+ and DATA_VALUE is the value which will trigger the watchpoint.
+ On exit, CONDITION_MODE will hold the enable bits for the DVC, and
+ CONDITION_VALUE will hold the value which should be put in the
+ DVC register. */
+static void
+calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value,
+ uint32_t *condition_mode, uint64_t *condition_value)
+{
+ int i, num_byte_enable, align_offset, num_bytes_off_dvc,
+ rightmost_enabled_byte;
+ CORE_ADDR addr_end_data, addr_end_dvc;
+
+ /* The DVC register compares bytes within fixed-length windows which
+ are word-aligned, with length equal to that of the DVC register.
+ We need to calculate where our watch region is relative to that
+ window and enable comparison of the bytes which fall within it. */
+
+ align_offset = addr % hwdebug_info.sizeof_condition;
+ addr_end_data = addr + len;
+ addr_end_dvc = (addr - align_offset
+ + hwdebug_info.sizeof_condition);
+ num_bytes_off_dvc = (addr_end_data > addr_end_dvc)?
+ addr_end_data - addr_end_dvc : 0;
+ num_byte_enable = len - num_bytes_off_dvc;
+ /* Here, bytes are numbered from right to left. */
+ rightmost_enabled_byte = (addr_end_data < addr_end_dvc)?
+ addr_end_dvc - addr_end_data : 0;
+
+ *condition_mode = PPC_BREAKPOINT_CONDITION_AND;
+ for (i = 0; i < num_byte_enable; i++)
+ *condition_mode
+ |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte);
+
+ /* Now we need to match the position within the DVC of the comparison
+ value with where the watch region is relative to the window
+ (i.e., the ALIGN_OFFSET). */
+
+ *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8
+ << rightmost_enabled_byte * 8);
+}
+
+/* Return the number of memory locations that need to be accessed to
+ evaluate the expression which generated the given value chain.
+ Returns -1 if there's any register access involved, or if there are
+ other kinds of values which are not acceptable in a condition
+ expression (e.g., lval_computed or lval_internalvar). */
+static int
+num_memory_accesses (const std::vector<value_ref_ptr> &chain)
+{
+ int found_memory_cnt = 0;
+
+ /* The idea here is that evaluating an expression generates a series
+ of values, one holding the value of every subexpression. (The
+ expression a*b+c has five subexpressions: a, b, a*b, c, and
+ a*b+c.) GDB's values hold almost enough information to establish
+ the criteria given above --- they identify memory lvalues,
+ register lvalues, computed values, etcetera. So we can evaluate
+ the expression, and then scan the chain of values that leaves
+ behind to determine the memory locations involved in the evaluation
+ of an expression.
+
+ However, I don't think that the values returned by inferior
+ function calls are special in any way. So this function may not
+ notice that an expression contains an inferior function call.
+ FIXME. */
+
+ for (const value_ref_ptr &iter : chain)
+ {
+ struct value *v = iter.get ();
+
+ /* Constants and values from the history are fine. */
+ if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0)
+ continue;
+ else if (VALUE_LVAL (v) == lval_memory)
+ {
+ /* A lazy memory lvalue is one that GDB never needed to fetch;
+ we either just used its address (e.g., `a' in `a.b') or
+ we never needed it at all (e.g., `a' in `a,b'). */
+ if (!value_lazy (v))
+ found_memory_cnt++;
+ }
+ /* Other kinds of values are not fine. */
+ else
+ return -1;
+ }
+
+ return found_memory_cnt;
+}
+
+/* Verifies whether the expression COND can be implemented using the
+ DVC (Data Value Compare) register in BookE processors. The expression
+ must test the watch value for equality with a constant expression.
+ If the function returns 1, DATA_VALUE will contain the constant against
+ which the watch value should be compared and LEN will contain the size
+ of the constant. */
+static int
+check_condition (CORE_ADDR watch_addr, struct expression *cond,
+ CORE_ADDR *data_value, int *len)
+{
+ int pc = 1, num_accesses_left, num_accesses_right;
+ struct value *left_val, *right_val;
+ std::vector<value_ref_ptr> left_chain, right_chain;
+
+ if (cond->elts[0].opcode != BINOP_EQUAL)
+ return 0;
+
+ fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0);
+ num_accesses_left = num_memory_accesses (left_chain);
+
+ if (left_val == NULL || num_accesses_left < 0)
+ return 0;
+
+ fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0);
+ num_accesses_right = num_memory_accesses (right_chain);
+
+ if (right_val == NULL || num_accesses_right < 0)
+ return 0;
+
+ if (num_accesses_left == 1 && num_accesses_right == 0
+ && VALUE_LVAL (left_val) == lval_memory
+ && value_address (left_val) == watch_addr)
+ {
+ *data_value = value_as_long (right_val);
+
+ /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
+ the same type as the memory region referenced by LEFT_VAL. */
+ *len = TYPE_LENGTH (check_typedef (value_type (left_val)));
+ }
+ else if (num_accesses_left == 0 && num_accesses_right == 1
+ && VALUE_LVAL (right_val) == lval_memory
+ && value_address (right_val) == watch_addr)
+ {
+ *data_value = value_as_long (left_val);
+
+ /* DATA_VALUE is the constant in LEFT_VAL, but actually has
+ the same type as the memory region referenced by RIGHT_VAL. */
+ *len = TYPE_LENGTH (check_typedef (value_type (right_val)));
+ }
+ else
+ return 0;
+
+ return 1;
+}
+
+/* Return non-zero if the target is capable of using hardware to evaluate
+ the condition expression, thus only triggering the watchpoint when it is
+ true. */
+bool
+ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr, int len,
+ int rw,
+ struct expression *cond)
+{
+ CORE_ADDR data_value;
+
+ return (have_ptrace_hwdebug_interface ()
+ && hwdebug_info.num_condition_regs > 0
+ && check_condition (addr, cond, &data_value, &len));
+}
+
+/* Set up P with the parameters necessary to request a watchpoint covering
+ LEN bytes starting at ADDR and if possible with condition expression COND
+ evaluated by hardware. INSERT tells if we are creating a request for
+ inserting or removing the watchpoint. */
+
+static void
+create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr,
+ int len, enum target_hw_bp_type type,
+ struct expression *cond, int insert)
+{
+ if (len == 1
+ || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE))
+ {
+ int use_condition;
+ CORE_ADDR data_value;
+
+ use_condition = (insert? can_use_watchpoint_cond_accel ()
+ : hwdebug_info.num_condition_regs > 0);
+ if (cond && use_condition && check_condition (addr, cond,
+ &data_value, &len))
+ calculate_dvc (addr, len, data_value, &p->condition_mode,
+ &p->condition_value);
+ else
+ {
+ p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+ p->condition_value = 0;
+ }
+
+ p->addr_mode = PPC_BREAKPOINT_MODE_EXACT;
+ p->addr2 = 0;
+ }
+ else
+ {
+ p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
+ p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+ p->condition_value = 0;
+
+ /* The watchpoint will trigger if the address of the memory access is
+ within the defined range, as follows: p->addr <= address < p->addr2.
+
+ Note that the above sentence just documents how ptrace interprets
+ its arguments; the watchpoint is set to watch the range defined by
+ the user _inclusively_, as specified by the user interface. */
+ p->addr2 = (uint64_t) addr + len;
+ }
+
+ p->version = PPC_DEBUG_CURRENT_VERSION;
+ p->trigger_type = get_trigger_type (type);
+ p->addr = (uint64_t) addr;
+}
+
+int
+ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
+ enum target_hw_bp_type type,
+ struct expression *cond)
+{
+ struct lwp_info *lp;
+ int ret = -1;
+
+ if (have_ptrace_hwdebug_interface ())
+ {
+ struct ppc_hw_breakpoint p;
+
+ create_watchpoint_request (&p, addr, len, type, cond, 1);
+
+ ALL_LWPS (lp)
+ hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
+
+ ret = 0;
+ }
+ else
+ {
+ long dabr_value;
+ long read_mode, write_mode;
+
+ if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
+ {
+ /* PowerPC 440 requires only the read/write flags to be passed
+ to the kernel. */
+ read_mode = 1;
+ write_mode = 2;
+ }
+ else
+ {
+ /* PowerPC 970 and other DABR-based processors are required to pass
+ the Breakpoint Translation bit together with the flags. */
+ read_mode = 5;
+ write_mode = 6;
+ }
+
+ dabr_value = addr & ~(read_mode | write_mode);
+ switch (type)
+ {
+ case hw_read:
+ /* Set read and translate bits. */
+ dabr_value |= read_mode;
+ break;
+ case hw_write:
+ /* Set write and translate bits. */
+ dabr_value |= write_mode;
+ break;
+ case hw_access:
+ /* Set read, write and translate bits. */
+ dabr_value |= read_mode | write_mode;
+ break;
+ }
+
+ saved_dabr_value = dabr_value;
+
+ ALL_LWPS (lp)
+ if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
+ saved_dabr_value) < 0)
+ return -1;
+
+ ret = 0;
+ }
+
+ return ret;
+}
+
+int
+ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
+ enum target_hw_bp_type type,
+ struct expression *cond)
+{
+ struct lwp_info *lp;
+ int ret = -1;
+
+ if (have_ptrace_hwdebug_interface ())
+ {
+ struct ppc_hw_breakpoint p;
+
+ create_watchpoint_request (&p, addr, len, type, cond, 0);
+
+ ALL_LWPS (lp)
+ hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
+
+ ret = 0;
+ }
+ else
+ {
+ saved_dabr_value = 0;
+ ALL_LWPS (lp)
+ if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
+ saved_dabr_value) < 0)
+ return -1;
+
+ ret = 0;
+ }
+
+ return ret;
+}
+
+void
+ppc_linux_nat_target::low_new_thread (struct lwp_info *lp)
+{
+ int tid = ptid_get_lwp (lp->ptid);
+
+ if (have_ptrace_hwdebug_interface ())
+ {
+ int i;
+ struct thread_points *p;
+ struct hw_break_tuple *hw_breaks;
+
+ if (VEC_empty (thread_points_p, ppc_threads))
+ return;
+
+ /* Get a list of breakpoints from any thread. */
+ p = VEC_last (thread_points_p, ppc_threads);
+ hw_breaks = p->hw_breaks;
+
+ /* Copy that thread's breakpoints and watchpoints to the new thread. */
+ for (i = 0; i < max_slots_number; i++)
+ if (hw_breaks[i].hw_break)
+ {
+ /* Older kernels did not make new threads inherit their parent
+ thread's debug state, so we always clear the slot and replicate
+ the debug state ourselves, ensuring compatibility with all
+ kernels. */
+
+ /* The ppc debug resource accounting is done through "slots".
+ Ask the kernel the deallocate this specific *point's slot. */
+ ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot);
+
+ hwdebug_insert_point (hw_breaks[i].hw_break, tid);
+ }
+ }
+ else
+ ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value);
+}
+
+static void
+ppc_linux_thread_exit (struct thread_info *tp, int silent)
+{
+ int i;
+ int tid = ptid_get_lwp (tp->ptid);
+ struct hw_break_tuple *hw_breaks;
+ struct thread_points *t = NULL, *p;
+
+ if (!have_ptrace_hwdebug_interface ())
+ return;
+
+ for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++)
+ if (p->tid == tid)
+ {
+ t = p;
+ break;
+ }
+
+ if (t == NULL)
+ return;
+
+ VEC_unordered_remove (thread_points_p, ppc_threads, i);
+
+ hw_breaks = t->hw_breaks;
+
+ for (i = 0; i < max_slots_number; i++)
+ if (hw_breaks[i].hw_break)
+ xfree (hw_breaks[i].hw_break);
+
+ xfree (t->hw_breaks);
+ xfree (t);
+}
+
+bool
+ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
+{
+ siginfo_t siginfo;
+
+ if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
+ return false;
+
+ if (siginfo.si_signo != SIGTRAP
+ || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
+ return false;
+
+ if (have_ptrace_hwdebug_interface ())
+ {
+ int i;
+ struct thread_points *t;
+ struct hw_break_tuple *hw_breaks;
+ /* The index (or slot) of the *point is passed in the si_errno field. */
+ int slot = siginfo.si_errno;
+
+ t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0);
+
+ /* Find out if this *point is a hardware breakpoint.
+ If so, we should return 0. */
+ if (t)
+ {
+ hw_breaks = t->hw_breaks;
+ for (i = 0; i < max_slots_number; i++)
+ if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot
+ && hw_breaks[i].hw_break->trigger_type
+ == PPC_BREAKPOINT_TRIGGER_EXECUTE)
+ return false;
+ }
+ }
+
+ *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
+ return true;
+}
+
+bool
+ppc_linux_nat_target::stopped_by_watchpoint ()
+{
+ CORE_ADDR addr;
+ return stopped_data_address (&addr);
+}
+
+bool
+ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr,
+ CORE_ADDR start,
+ int length)
+{
+ int mask;
+
+ if (have_ptrace_hwdebug_interface ()
+ && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
+ return start <= addr && start + length >= addr;
+ else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
+ mask = 3;
+ else
+ mask = 7;
+
+ addr &= ~mask;
+
+ /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
+ return start <= addr + mask && start + length - 1 >= addr;
+}
+
+/* Return the number of registers needed for a masked hardware watchpoint. */
+
+int
+ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr, CORE_ADDR mask)
+{
+ if (!have_ptrace_hwdebug_interface ()
+ || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0)
+ return -1;
+ else if ((mask & 0xC0000000) != 0xC0000000)
+ {
+ warning (_("The given mask covers kernel address space "
+ "and cannot be used.\n"));
+
+ return -2;
+ }
+ else
+ return 2;
+}
+
+void
+ppc_linux_nat_target::store_registers (struct regcache *regcache, int regno)
+{
+ pid_t tid = get_ptrace_pid (regcache_get_ptid (regcache));