-/* Table of register aliases. */
-
-static const struct riscv_register_alias riscv_register_aliases[] =
-{
- /* Aliases for general purpose registers. These are the architectural
- names, as GDB uses the more user friendly names by default. */
- { "x0", (RISCV_ZERO_REGNUM + 0) },
- { "x1", (RISCV_ZERO_REGNUM + 1) },
- { "x2", (RISCV_ZERO_REGNUM + 2) },
- { "x3", (RISCV_ZERO_REGNUM + 3) },
- { "x4", (RISCV_ZERO_REGNUM + 4) },
- { "x5", (RISCV_ZERO_REGNUM + 5) },
- { "x6", (RISCV_ZERO_REGNUM + 6) },
- { "x7", (RISCV_ZERO_REGNUM + 7) },
- { "x8", (RISCV_ZERO_REGNUM + 8) },
- { "s0", (RISCV_ZERO_REGNUM + 8) }, /* fp, s0, and x8 are all aliases. */
- { "x9", (RISCV_ZERO_REGNUM + 9) },
- { "x10", (RISCV_ZERO_REGNUM + 10) },
- { "x11", (RISCV_ZERO_REGNUM + 11) },
- { "x12", (RISCV_ZERO_REGNUM + 12) },
- { "x13", (RISCV_ZERO_REGNUM + 13) },
- { "x14", (RISCV_ZERO_REGNUM + 14) },
- { "x15", (RISCV_ZERO_REGNUM + 15) },
- { "x16", (RISCV_ZERO_REGNUM + 16) },
- { "x17", (RISCV_ZERO_REGNUM + 17) },
- { "x18", (RISCV_ZERO_REGNUM + 18) },
- { "x19", (RISCV_ZERO_REGNUM + 19) },
- { "x20", (RISCV_ZERO_REGNUM + 20) },
- { "x21", (RISCV_ZERO_REGNUM + 21) },
- { "x22", (RISCV_ZERO_REGNUM + 22) },
- { "x23", (RISCV_ZERO_REGNUM + 23) },
- { "x24", (RISCV_ZERO_REGNUM + 24) },
- { "x25", (RISCV_ZERO_REGNUM + 25) },
- { "x26", (RISCV_ZERO_REGNUM + 26) },
- { "x27", (RISCV_ZERO_REGNUM + 27) },
- { "x28", (RISCV_ZERO_REGNUM + 28) },
- { "x29", (RISCV_ZERO_REGNUM + 29) },
- { "x30", (RISCV_ZERO_REGNUM + 30) },
- { "x31", (RISCV_ZERO_REGNUM + 31) },
-
- /* Aliases for the floating-point registers. These are the architectural
- names as GDB uses the more user friendly names by default. */
- { "f0", (RISCV_FIRST_FP_REGNUM + 0) },
- { "f1", (RISCV_FIRST_FP_REGNUM + 1) },
- { "f2", (RISCV_FIRST_FP_REGNUM + 2) },
- { "f3", (RISCV_FIRST_FP_REGNUM + 3) },
- { "f4", (RISCV_FIRST_FP_REGNUM + 4) },
- { "f5", (RISCV_FIRST_FP_REGNUM + 5) },
- { "f6", (RISCV_FIRST_FP_REGNUM + 6) },
- { "f7", (RISCV_FIRST_FP_REGNUM + 7) },
- { "f8", (RISCV_FIRST_FP_REGNUM + 8) },
- { "f9", (RISCV_FIRST_FP_REGNUM + 9) },
- { "f10", (RISCV_FIRST_FP_REGNUM + 10) },
- { "f11", (RISCV_FIRST_FP_REGNUM + 11) },
- { "f12", (RISCV_FIRST_FP_REGNUM + 12) },
- { "f13", (RISCV_FIRST_FP_REGNUM + 13) },
- { "f14", (RISCV_FIRST_FP_REGNUM + 14) },
- { "f15", (RISCV_FIRST_FP_REGNUM + 15) },
- { "f16", (RISCV_FIRST_FP_REGNUM + 16) },
- { "f17", (RISCV_FIRST_FP_REGNUM + 17) },
- { "f18", (RISCV_FIRST_FP_REGNUM + 18) },
- { "f19", (RISCV_FIRST_FP_REGNUM + 19) },
- { "f20", (RISCV_FIRST_FP_REGNUM + 20) },
- { "f21", (RISCV_FIRST_FP_REGNUM + 21) },
- { "f22", (RISCV_FIRST_FP_REGNUM + 22) },
- { "f23", (RISCV_FIRST_FP_REGNUM + 23) },
- { "f24", (RISCV_FIRST_FP_REGNUM + 24) },
- { "f25", (RISCV_FIRST_FP_REGNUM + 25) },
- { "f26", (RISCV_FIRST_FP_REGNUM + 26) },
- { "f27", (RISCV_FIRST_FP_REGNUM + 27) },
- { "f28", (RISCV_FIRST_FP_REGNUM + 28) },
- { "f29", (RISCV_FIRST_FP_REGNUM + 29) },
- { "f30", (RISCV_FIRST_FP_REGNUM + 30) },
- { "f31", (RISCV_FIRST_FP_REGNUM + 31) },
+/* The general x-registers feature set. */
+
+static const struct riscv_register_feature riscv_xreg_feature =
+{
+ "org.gnu.gdb.riscv.cpu",
+ {
+ { RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, true },
+ { RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, true },
+ { RISCV_ZERO_REGNUM + 2, { "sp", "x2" }, true },
+ { RISCV_ZERO_REGNUM + 3, { "gp", "x3" }, true },
+ { RISCV_ZERO_REGNUM + 4, { "tp", "x4" }, true },
+ { RISCV_ZERO_REGNUM + 5, { "t0", "x5" }, true },
+ { RISCV_ZERO_REGNUM + 6, { "t1", "x6" }, true },
+ { RISCV_ZERO_REGNUM + 7, { "t2", "x7" }, true },
+ { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" }, true },
+ { RISCV_ZERO_REGNUM + 9, { "s1", "x9" }, true },
+ { RISCV_ZERO_REGNUM + 10, { "a0", "x10" }, true },
+ { RISCV_ZERO_REGNUM + 11, { "a1", "x11" }, true },
+ { RISCV_ZERO_REGNUM + 12, { "a2", "x12" }, true },
+ { RISCV_ZERO_REGNUM + 13, { "a3", "x13" }, true },
+ { RISCV_ZERO_REGNUM + 14, { "a4", "x14" }, true },
+ { RISCV_ZERO_REGNUM + 15, { "a5", "x15" }, true },
+ { RISCV_ZERO_REGNUM + 16, { "a6", "x16" }, true },
+ { RISCV_ZERO_REGNUM + 17, { "a7", "x17" }, true },
+ { RISCV_ZERO_REGNUM + 18, { "s2", "x18" }, true },
+ { RISCV_ZERO_REGNUM + 19, { "s3", "x19" }, true },
+ { RISCV_ZERO_REGNUM + 20, { "s4", "x20" }, true },
+ { RISCV_ZERO_REGNUM + 21, { "s5", "x21" }, true },
+ { RISCV_ZERO_REGNUM + 22, { "s6", "x22" }, true },
+ { RISCV_ZERO_REGNUM + 23, { "s7", "x23" }, true },
+ { RISCV_ZERO_REGNUM + 24, { "s8", "x24" }, true },
+ { RISCV_ZERO_REGNUM + 25, { "s9", "x25" }, true },
+ { RISCV_ZERO_REGNUM + 26, { "s10", "x26" }, true },
+ { RISCV_ZERO_REGNUM + 27, { "s11", "x27" }, true },
+ { RISCV_ZERO_REGNUM + 28, { "t3", "x28" }, true },
+ { RISCV_ZERO_REGNUM + 29, { "t4", "x29" }, true },
+ { RISCV_ZERO_REGNUM + 30, { "t5", "x30" }, true },
+ { RISCV_ZERO_REGNUM + 31, { "t6", "x31" }, true },
+ { RISCV_ZERO_REGNUM + 32, { "pc" }, true }
+ }