- /* STMG r1, r3, d2(b2) --- store multiple (64-bit version) */
- else if (word_size == 8
- && is_rsy (insn, op1_stmg, op2_stmg, &r1, &r3, &d2, &b2))
- {
- int regnum;
- int offset;
- struct prologue_value addr;
-
- for (regnum = r1, offset = 0;
- regnum <= r3;
- regnum++, offset += 8)
- {
- compute_x_addr (&addr, data->gpr, d2 + offset, 0, b2);
- s390_store (&addr, 8, &data->gpr[regnum], data);
- }
- }
-
- /* AHI r1, i2 --- add halfword immediate */
- else if (word_size == 4
- && is_ri (insn, op1_ahi, op2_ahi, &r1, &i2))
- pv_add_constant (&data->gpr[r1], i2);
-
- /* AGHI r1, i2 --- add halfword immediate (64-bit version) */
- else if (word_size == 8
- && is_ri (insn, op1_aghi, op2_aghi, &r1, &i2))
- pv_add_constant (&data->gpr[r1], i2);
-
- /* AFI r1, i2 --- add fullword immediate */
- else if (word_size == 4
- && is_ril (insn, op1_afi, op2_afi, &r1, &i2))
- pv_add_constant (&data->gpr[r1], i2);
-
- /* AGFI r1, i2 --- add fullword immediate (64-bit version) */
- else if (word_size == 8
- && is_ril (insn, op1_agfi, op2_agfi, &r1, &i2))
- pv_add_constant (&data->gpr[r1], i2);
-
- /* ALFI r1, i2 --- add logical immediate */
- else if (word_size == 4
- && is_ril (insn, op1_alfi, op2_alfi, &r1, &i2))
- pv_add_constant (&data->gpr[r1], (CORE_ADDR)i2 & 0xffffffff);
-
- /* ALGFI r1, i2 --- add logical immediate (64-bit version) */
- else if (word_size == 8
- && is_ril (insn, op1_algfi, op2_algfi, &r1, &i2))
- pv_add_constant (&data->gpr[r1], (CORE_ADDR)i2 & 0xffffffff);
-
- /* AR r1, r2 -- add register */
- else if (word_size == 4
- && is_rr (insn, op_ar, &r1, &r2))
- pv_add (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
-
- /* AGR r1, r2 -- add register (64-bit version) */
- else if (word_size == 8
- && is_rre (insn, op_agr, &r1, &r2))
- pv_add (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
-
- /* A r1, d2(x2, b2) -- add */
- else if (word_size == 4
- && is_rx (insn, op_a, &r1, &d2, &x2, &b2))
- {
- struct prologue_value addr;
- struct prologue_value value;
-
- compute_x_addr (&addr, data->gpr, d2, x2, b2);
- s390_load (&addr, 4, &value, data);
-
- pv_add (&data->gpr[r1], &data->gpr[r1], &value);
- }
-
- /* AY r1, d2(x2, b2) -- add (long-displacement version) */
- else if (word_size == 4
- && is_rxy (insn, op1_ay, op2_ay, &r1, &d2, &x2, &b2))
- {
- struct prologue_value addr;
- struct prologue_value value;
-
- compute_x_addr (&addr, data->gpr, d2, x2, b2);
- s390_load (&addr, 4, &value, data);
-
- pv_add (&data->gpr[r1], &data->gpr[r1], &value);
- }
-
- /* AG r1, d2(x2, b2) -- add (64-bit version) */
- else if (word_size == 8
- && is_rxy (insn, op1_ag, op2_ag, &r1, &d2, &x2, &b2))
- {
- struct prologue_value addr;
- struct prologue_value value;
-
- compute_x_addr (&addr, data->gpr, d2, x2, b2);
- s390_load (&addr, 8, &value, data);
-
- pv_add (&data->gpr[r1], &data->gpr[r1], &value);
- }
-
- /* SLFI r1, i2 --- subtract logical immediate */
- else if (word_size == 4
- && is_ril (insn, op1_slfi, op2_slfi, &r1, &i2))
- pv_add_constant (&data->gpr[r1], -((CORE_ADDR)i2 & 0xffffffff));
-
- /* SLGFI r1, i2 --- subtract logical immediate (64-bit version) */
- else if (word_size == 8
- && is_ril (insn, op1_slgfi, op2_slgfi, &r1, &i2))
- pv_add_constant (&data->gpr[r1], -((CORE_ADDR)i2 & 0xffffffff));
-
- /* SR r1, r2 -- subtract register */
- else if (word_size == 4
- && is_rr (insn, op_sr, &r1, &r2))
- pv_subtract (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
-
- /* SGR r1, r2 -- subtract register (64-bit version) */
- else if (word_size == 8
- && is_rre (insn, op_sgr, &r1, &r2))
- pv_subtract (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
-
- /* S r1, d2(x2, b2) -- subtract */
- else if (word_size == 4
- && is_rx (insn, op_s, &r1, &d2, &x2, &b2))
- {
- struct prologue_value addr;
- struct prologue_value value;
-
- compute_x_addr (&addr, data->gpr, d2, x2, b2);
- s390_load (&addr, 4, &value, data);
-
- pv_subtract (&data->gpr[r1], &data->gpr[r1], &value);
- }
-
- /* SY r1, d2(x2, b2) -- subtract (long-displacement version) */
- else if (word_size == 4
- && is_rxy (insn, op1_sy, op2_sy, &r1, &d2, &x2, &b2))
- {
- struct prologue_value addr;
- struct prologue_value value;
-
- compute_x_addr (&addr, data->gpr, d2, x2, b2);
- s390_load (&addr, 4, &value, data);
-
- pv_subtract (&data->gpr[r1], &data->gpr[r1], &value);
- }
-
- /* SG r1, d2(x2, b2) -- subtract (64-bit version) */
- else if (word_size == 8
- && is_rxy (insn, op1_sg, op2_sg, &r1, &d2, &x2, &b2))
- {
- struct prologue_value addr;
- struct prologue_value value;
-
- compute_x_addr (&addr, data->gpr, d2, x2, b2);
- s390_load (&addr, 8, &value, data);
-
- pv_subtract (&data->gpr[r1], &data->gpr[r1], &value);
- }
-
- /* NR r1, r2 --- logical and */
- else if (word_size == 4
- && is_rr (insn, op_nr, &r1, &r2))
- pv_logical_and (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
-
- /* NGR r1, r2 >--- logical and (64-bit version) */
- else if (word_size == 8
- && is_rre (insn, op_ngr, &r1, &r2))
- pv_logical_and (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
-
- /* LA r1, d2(x2, b2) --- load address */
- else if (is_rx (insn, op_la, &r1, &d2, &x2, &b2))
- compute_x_addr (&data->gpr[r1], data->gpr, d2, x2, b2);
-
- /* LAY r1, d2(x2, b2) --- load address (long-displacement version) */
- else if (is_rxy (insn, op1_lay, op2_lay, &r1, &d2, &x2, &b2))
- compute_x_addr (&data->gpr[r1], data->gpr, d2, x2, b2);
-
- /* LARL r1, i2 --- load address relative long */
+ /* AHI r1, i2 --- add halfword immediate. */
+ /* AGHI r1, i2 --- add halfword immediate (64-bit version). */
+ /* AFI r1, i2 --- add fullword immediate. */
+ /* AGFI r1, i2 --- add fullword immediate (64-bit version). */
+ else if (is_ri (insn32, op1_ahi, op2_ahi, &r1, &i2)
+ || is_ri (insn64, op1_aghi, op2_aghi, &r1, &i2)
+ || is_ril (insn32, op1_afi, op2_afi, &r1, &i2)
+ || is_ril (insn64, op1_agfi, op2_agfi, &r1, &i2))
+ data->gpr[r1] = pv_add_constant (data->gpr[r1], i2);
+
+ /* ALFI r1, i2 --- add logical immediate. */
+ /* ALGFI r1, i2 --- add logical immediate (64-bit version). */
+ else if (is_ril (insn32, op1_alfi, op2_alfi, &r1, &i2)
+ || is_ril (insn64, op1_algfi, op2_algfi, &r1, &i2))
+ data->gpr[r1] = pv_add_constant (data->gpr[r1],
+ (CORE_ADDR)i2 & 0xffffffff);
+
+ /* AR r1, r2 -- add register. */
+ /* AGR r1, r2 -- add register (64-bit version). */
+ else if (is_rr (insn32, op_ar, &r1, &r2)
+ || is_rre (insn64, op_agr, &r1, &r2))
+ data->gpr[r1] = pv_add (data->gpr[r1], data->gpr[r2]);
+
+ /* A r1, d2(x2, b2) -- add. */
+ /* AY r1, d2(x2, b2) -- add (long-displacement version). */
+ /* AG r1, d2(x2, b2) -- add (64-bit version). */
+ else if (is_rx (insn32, op_a, &r1, &d2, &x2, &b2)
+ || is_rxy (insn32, op1_ay, op2_ay, &r1, &d2, &x2, &b2)
+ || is_rxy (insn64, op1_ag, op2_ag, &r1, &d2, &x2, &b2))
+ data->gpr[r1] = pv_add (data->gpr[r1],
+ s390_load (data, d2, x2, b2, data->gpr_size));
+
+ /* SLFI r1, i2 --- subtract logical immediate. */
+ /* SLGFI r1, i2 --- subtract logical immediate (64-bit version). */
+ else if (is_ril (insn32, op1_slfi, op2_slfi, &r1, &i2)
+ || is_ril (insn64, op1_slgfi, op2_slgfi, &r1, &i2))
+ data->gpr[r1] = pv_add_constant (data->gpr[r1],
+ -((CORE_ADDR)i2 & 0xffffffff));
+
+ /* SR r1, r2 -- subtract register. */
+ /* SGR r1, r2 -- subtract register (64-bit version). */
+ else if (is_rr (insn32, op_sr, &r1, &r2)
+ || is_rre (insn64, op_sgr, &r1, &r2))
+ data->gpr[r1] = pv_subtract (data->gpr[r1], data->gpr[r2]);
+
+ /* S r1, d2(x2, b2) -- subtract. */
+ /* SY r1, d2(x2, b2) -- subtract (long-displacement version). */
+ /* SG r1, d2(x2, b2) -- subtract (64-bit version). */
+ else if (is_rx (insn32, op_s, &r1, &d2, &x2, &b2)
+ || is_rxy (insn32, op1_sy, op2_sy, &r1, &d2, &x2, &b2)
+ || is_rxy (insn64, op1_sg, op2_sg, &r1, &d2, &x2, &b2))
+ data->gpr[r1] = pv_subtract (data->gpr[r1],
+ s390_load (data, d2, x2, b2, data->gpr_size));
+
+ /* LA r1, d2(x2, b2) --- load address. */
+ /* LAY r1, d2(x2, b2) --- load address (long-displacement version). */
+ else if (is_rx (insn, op_la, &r1, &d2, &x2, &b2)
+ || is_rxy (insn, op1_lay, op2_lay, &r1, &d2, &x2, &b2))
+ data->gpr[r1] = s390_addr (data, d2, x2, b2);
+
+ /* LARL r1, i2 --- load address relative long. */