+ *r1 = (insn[1] >> 4) & 0xf;
+ /* i2 is a 16-bit signed quantity. */
+ *i2 = (((insn[2] << 8) | insn[3]) ^ 0x8000) - 0x8000;
+ return 1;
+ }
+ else
+ return 0;
+}
+
+
+static int
+is_ril (bfd_byte *insn, int op1, int op2,
+ unsigned int *r1, int *i2)
+{
+ if (insn[0] == op1 && (insn[1] & 0xf) == op2)
+ {
+ *r1 = (insn[1] >> 4) & 0xf;
+ /* i2 is a signed quantity. If the host 'int' is 32 bits long,
+ no sign extension is necessary, but we don't want to assume
+ that. */
+ *i2 = (((insn[2] << 24)
+ | (insn[3] << 16)
+ | (insn[4] << 8)
+ | (insn[5])) ^ 0x80000000) - 0x80000000;
+ return 1;
+ }
+ else
+ return 0;
+}
+
+
+static int
+is_rr (bfd_byte *insn, int op, unsigned int *r1, unsigned int *r2)
+{
+ if (insn[0] == op)
+ {
+ *r1 = (insn[1] >> 4) & 0xf;
+ *r2 = insn[1] & 0xf;
+ return 1;
+ }
+ else
+ return 0;
+}
+
+
+static int
+is_rre (bfd_byte *insn, int op, unsigned int *r1, unsigned int *r2)
+{
+ if (((insn[0] << 8) | insn[1]) == op)
+ {
+ /* Yes, insn[3]. insn[2] is unused in RRE format. */
+ *r1 = (insn[3] >> 4) & 0xf;
+ *r2 = insn[3] & 0xf;
+ return 1;
+ }
+ else
+ return 0;
+}
+
+
+static int
+is_rs (bfd_byte *insn, int op,
+ unsigned int *r1, unsigned int *r3, unsigned int *d2, unsigned int *b2)
+{
+ if (insn[0] == op)
+ {
+ *r1 = (insn[1] >> 4) & 0xf;
+ *r3 = insn[1] & 0xf;
+ *b2 = (insn[2] >> 4) & 0xf;
+ *d2 = ((insn[2] & 0xf) << 8) | insn[3];
+ return 1;
+ }
+ else
+ return 0;
+}
+
+
+static int
+is_rse (bfd_byte *insn, int op1, int op2,
+ unsigned int *r1, unsigned int *r3, unsigned int *d2, unsigned int *b2)
+{
+ if (insn[0] == op1
+ /* Yes, insn[5]. insn[4] is unused. */
+ && insn[5] == op2)
+ {
+ *r1 = (insn[1] >> 4) & 0xf;
+ *r3 = insn[1] & 0xf;
+ *b2 = (insn[2] >> 4) & 0xf;
+ *d2 = ((insn[2] & 0xf) << 8) | insn[3];
+ return 1;
+ }
+ else
+ return 0;
+}
+
+
+static int
+is_rx (bfd_byte *insn, int op,
+ unsigned int *r1, unsigned int *d2, unsigned int *x2, unsigned int *b2)
+{
+ if (insn[0] == op)
+ {
+ *r1 = (insn[1] >> 4) & 0xf;
+ *x2 = insn[1] & 0xf;
+ *b2 = (insn[2] >> 4) & 0xf;
+ *d2 = ((insn[2] & 0xf) << 8) | insn[3];
+ return 1;
+ }
+ else
+ return 0;
+}
+
+
+static int
+is_rxe (bfd_byte *insn, int op1, int op2,
+ unsigned int *r1, unsigned int *d2, unsigned int *x2, unsigned int *b2)
+{
+ if (insn[0] == op1
+ /* Yes, insn[5]. insn[4] is unused. */
+ && insn[5] == op2)
+ {
+ *r1 = (insn[1] >> 4) & 0xf;
+ *x2 = insn[1] & 0xf;
+ *b2 = (insn[2] >> 4) & 0xf;
+ *d2 = ((insn[2] & 0xf) << 8) | insn[3];
+ return 1;
+ }
+ else
+ return 0;
+}
+
+
+/* Set ADDR to the effective address for an X-style instruction, like:
+
+ L R1, D2(X2, B2)
+
+ Here, X2 and B2 are registers, and D2 is an unsigned 12-bit
+ constant; the effective address is the sum of all three. If either
+ X2 or B2 are zero, then it doesn't contribute to the sum --- this
+ means that r0 can't be used as either X2 or B2.
+
+ GPR is an array of general register values, indexed by GPR number,
+ not GDB register number. */
+static void
+compute_x_addr (struct prologue_value *addr,
+ struct prologue_value *gpr,
+ unsigned int d2, unsigned int x2, unsigned int b2)
+{
+ /* We can't just add stuff directly in addr; it might alias some of
+ the registers we need to read. */
+ struct prologue_value result;
+
+ pv_set_to_constant (&result, d2);
+ if (x2)
+ pv_add (&result, &result, &gpr[x2]);
+ if (b2)
+ pv_add (&result, &result, &gpr[b2]);
+
+ *addr = result;
+}
+
+
+/* The number of GPR and FPR spill slots in an S/390 stack frame. We
+ track general-purpose registers r2 -- r15, and floating-point
+ registers f0, f2, f4, and f6. */
+#define S390_NUM_SPILL_SLOTS (14 + 4)
+
+
+/* If the SIZE bytes at ADDR are a stack slot we're actually tracking,
+ return pv_definite_yes and set *STACK to point to the slot. If
+ we're sure that they are not any of our stack slots, then return
+ pv_definite_no. Otherwise, return pv_maybe.
+ - GPR is an array indexed by GPR number giving the current values
+ of the general-purpose registers.
+ - SPILL is an array tracking the spill area of the caller's frame;
+ SPILL[i] is the i'th spill slot. The spill slots are designated
+ for r2 -- r15, and then f0, f2, f4, and f6.
+ - BACK_CHAIN is the value of the back chain slot; it's only valid
+ when the current frame actually has some space for a back chain
+ slot --- that is, when the current value of the stack pointer
+ (according to GPR) is at least S390_STACK_FRAME_OVERHEAD bytes
+ less than its original value. */
+static enum pv_boolean
+s390_on_stack (struct prologue_value *addr,
+ CORE_ADDR size,
+ struct prologue_value *gpr,
+ struct prologue_value *spill,
+ struct prologue_value *back_chain,
+ struct prologue_value **stack)
+{
+ struct prologue_value gpr_spill_addr;
+ struct prologue_value fpr_spill_addr;
+ struct prologue_value back_chain_addr;
+ int i;
+ enum pv_boolean b;
+
+ /* Construct the addresses of the spill arrays and the back chain. */
+ pv_set_to_register (&gpr_spill_addr, S390_SP_REGNUM, 2 * S390_GPR_SIZE);
+ pv_set_to_register (&fpr_spill_addr, S390_SP_REGNUM, 16 * S390_GPR_SIZE);
+ back_chain_addr = gpr[S390_SP_REGNUM - S390_GP0_REGNUM];
+
+ /* We have to check for GPR and FPR references using two separate
+ calls to pv_is_array_ref, since the GPR and FPR spill slots are
+ different sizes. (SPILL is an array, but the thing it tracks
+ isn't really an array.) */
+
+ /* Was it a reference to the GPR spill array? */
+ b = pv_is_array_ref (addr, size, &gpr_spill_addr, 14, S390_GPR_SIZE, &i);
+ if (b == pv_definite_yes)
+ {
+ *stack = &spill[i];
+ return pv_definite_yes;
+ }
+ if (b == pv_maybe)
+ return pv_maybe;
+
+ /* Was it a reference to the FPR spill array? */
+ b = pv_is_array_ref (addr, size, &fpr_spill_addr, 4, S390_FPR_SIZE, &i);
+ if (b == pv_definite_yes)
+ {
+ *stack = &spill[14 + i];
+ return pv_definite_yes;
+ }
+ if (b == pv_maybe)
+ return pv_maybe;
+
+ /* Was it a reference to the back chain?
+ This isn't quite right. We ought to check whether we have
+ actually allocated any new frame at all. */
+ b = pv_is_array_ref (addr, size, &back_chain_addr, 1, S390_GPR_SIZE, &i);
+ if (b == pv_definite_yes)
+ {
+ *stack = back_chain;
+ return pv_definite_yes;
+ }
+ if (b == pv_maybe)
+ return pv_maybe;
+
+ /* All the above queries returned definite 'no's. */
+ return pv_definite_no;
+}
+
+
+/* Do a SIZE-byte store of VALUE to ADDR. GPR, SPILL, and BACK_CHAIN,
+ and the return value are as described for s390_on_stack, above.
+ Note that, when this returns pv_maybe, we have to assume that all
+ of our memory now contains unknown values. */
+static enum pv_boolean
+s390_store (struct prologue_value *addr,
+ CORE_ADDR size,
+ struct prologue_value *value,
+ struct prologue_value *gpr,
+ struct prologue_value *spill,
+ struct prologue_value *back_chain)
+{
+ struct prologue_value *stack;
+ enum pv_boolean on_stack
+ = s390_on_stack (addr, size, gpr, spill, back_chain, &stack);
+
+ if (on_stack == pv_definite_yes)
+ *stack = *value;
+
+ return on_stack;
+}
+
+
+/* The current frame looks like a signal delivery frame: the first
+ instruction is an 'svc' opcode. If the next frame is a signal
+ handler's frame, set FI's saved register map to point into the
+ signal context structure. */
+static void
+s390_get_signal_frame_info (struct frame_info *fi)
+{
+ struct frame_info *next_frame = get_next_frame (fi);
+
+ if (next_frame
+ && get_frame_extra_info (next_frame)
+ && get_frame_extra_info (next_frame)->sigcontext)
+ {
+ /* We're definitely backtracing from a signal handler. */
+ CORE_ADDR *saved_regs = deprecated_get_frame_saved_regs (fi);
+ CORE_ADDR save_reg_addr = (get_frame_extra_info (next_frame)->sigcontext
+ + DEPRECATED_REGISTER_BYTE (S390_GP0_REGNUM));
+ int reg;
+
+ for (reg = 0; reg < S390_NUM_GPRS; reg++)
+ {
+ saved_regs[S390_GP0_REGNUM + reg] = save_reg_addr;
+ save_reg_addr += S390_GPR_SIZE;
+ }
+
+ save_reg_addr = (get_frame_extra_info (next_frame)->sigcontext
+ + (GDB_TARGET_IS_ESAME ? S390X_SIGREGS_FP0_OFFSET :
+ S390_SIGREGS_FP0_OFFSET));
+ for (reg = 0; reg < S390_NUM_FPRS; reg++)
+ {
+ saved_regs[S390_FP0_REGNUM + reg] = save_reg_addr;
+ save_reg_addr += S390_FPR_SIZE;
+ }
+ }
+}
+
+
+static int
+s390_get_frame_info (CORE_ADDR start_pc,
+ struct frame_extra_info *fextra_info,
+ struct frame_info *fi,
+ int init_extra_info)
+{
+ /* Our return value:
+ zero if we were able to read all the instructions we wanted, or
+ -1 if we got an error trying to read memory. */
+ int result = 0;
+
+ /* The current PC for our abstract interpretation. */
+ CORE_ADDR pc;
+
+ /* The address of the next instruction after that. */
+ CORE_ADDR next_pc;
+
+ /* The general-purpose registers. */
+ struct prologue_value gpr[S390_NUM_GPRS];
+
+ /* The floating-point registers. */
+ struct prologue_value fpr[S390_NUM_FPRS];
+
+ /* The register spill stack slots in the caller's frame ---
+ general-purpose registers r2 through r15, and floating-point
+ registers. spill[i] is where gpr i+2 gets spilled;
+ spill[(14, 15, 16, 17)] is where (f0, f2, f4, f6) get spilled. */
+ struct prologue_value spill[S390_NUM_SPILL_SLOTS];
+
+ /* The value of the back chain slot. This is only valid if the stack
+ pointer is known to be less than its original value --- that is,
+ if we have indeed allocated space on the stack. */
+ struct prologue_value back_chain;
+
+ /* The address of the instruction after the last one that changed
+ the SP, FP, or back chain. */
+ CORE_ADDR after_last_frame_setup_insn = start_pc;
+
+ /* Set up everything's initial value. */
+ {
+ int i;
+
+ for (i = 0; i < S390_NUM_GPRS; i++)
+ pv_set_to_register (&gpr[i], S390_GP0_REGNUM + i, 0);
+
+ for (i = 0; i < S390_NUM_FPRS; i++)
+ pv_set_to_register (&fpr[i], S390_FP0_REGNUM + i, 0);
+
+ for (i = 0; i < S390_NUM_SPILL_SLOTS; i++)
+ pv_set_to_unknown (&spill[i]);
+
+ pv_set_to_unknown (&back_chain);
+ }
+
+ /* Start interpreting instructions, until we hit something we don't
+ know how to interpret. (Ideally, we should stop at the frame's
+ real current PC, but at the moment, our callers don't give us
+ that info.) */
+ for (pc = start_pc; ; pc = next_pc)
+ {
+ bfd_byte insn[S390_MAX_INSTR_SIZE];
+ int insn_len = s390_readinstruction (insn, pc);
+
+ /* Fields for various kinds of instructions. */
+ unsigned int b2, r1, r2, d2, x2, r3;
+ int i2;
+
+ /* The values of SP, FP, and back chain before this instruction,
+ for detecting instructions that change them. */
+ struct prologue_value pre_insn_sp, pre_insn_fp, pre_insn_back_chain;
+
+ /* If we got an error trying to read the instruction, report it. */
+ if (insn_len < 0)
+ {
+ result = -1;
+ break;
+ }
+
+ next_pc = pc + insn_len;
+
+ pre_insn_sp = gpr[S390_SP_REGNUM - S390_GP0_REGNUM];
+ pre_insn_fp = gpr[S390_FRAME_REGNUM - S390_GP0_REGNUM];
+ pre_insn_back_chain = back_chain;
+
+ /* A special case, first --- only recognized as the very first
+ instruction of the function, for signal delivery frames:
+ SVC i --- system call */
+ if (pc == start_pc
+ && is_rr (insn, op_svc, &r1, &r2))
+ {
+ if (fi)
+ s390_get_signal_frame_info (fi);
+ break;
+ }
+
+ /* AHI r1, i2 --- add halfword immediate */
+ else if (is_ri (insn, op1_ahi, op2_ahi, &r1, &i2))
+ pv_add_constant (&gpr[r1], i2);