+ /* Watch out! saved_regs is only for the real registers, and
+ doesn't include space for the pseudo registers. */
+ fi->saved_regs[register_number]= fi->frame - where[rn] + depth;
+
+ }
+ else
+ fi->saved_regs[register_number] = 0;
+ }
+
+ if (have_fp)
+ {
+ /* SP_REGNUM is 15. For shmedia 15 is the real register. For
+ shcompact 15 is the arch register corresponding to the pseudo
+ register r15 which still is the SP register. */
+ /* The place on the stack where fp is stored contains the sp of
+ the caller. */
+ /* Again, saved_registers contains only space for the real registers,
+ so we store in FP_REGNUM position. */
+ int size;
+ if (tdep->sh_abi == SH_ABI_32)
+ size = 4;
+ else
+ size = REGISTER_RAW_SIZE (fp_regnum);
+ fi->saved_regs[sp_regnum] = read_memory_integer (fi->saved_regs[fp_regnum], size);
+ }
+ else
+ fi->saved_regs[sp_regnum] = fi->frame;
+
+ fi->extra_info->f_offset = depth - where[fp_regnum];
+}
+
+static void
+sh_fp_frame_init_saved_regs (struct frame_info *fi)
+{
+ int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
+ int rn;
+ int have_fp = 0;
+ int depth;
+ int pc;
+ int opc;
+ int insn;
+ int r3_val = 0;
+ char *dummy_regs = deprecated_generic_find_dummy_frame (fi->pc, fi->frame);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (fi->saved_regs == NULL)
+ frame_saved_regs_zalloc (fi);
+ else
+ memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
+
+ if (dummy_regs)
+ {
+ /* DANGER! This is ONLY going to work if the char buffer format of
+ the saved registers is byte-for-byte identical to the
+ CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
+ memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
+ return;
+ }
+
+ fi->extra_info->leaf_function = 1;
+ fi->extra_info->f_offset = 0;
+
+ for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
+ where[rn] = -1;
+
+ depth = 0;
+
+ /* Loop around examining the prologue insns until we find something
+ that does not appear to be part of the prologue. But give up
+ after 20 of them, since we're getting silly then. */
+
+ pc = get_pc_function_start (fi->pc);
+ if (!pc)
+ {
+ fi->pc = 0;
+ return;
+ }
+
+ for (opc = pc + (2 * 28); pc < opc; pc += 2)
+ {
+ insn = read_memory_integer (pc, 2);
+ /* See where the registers will be saved to */
+ if (IS_PUSH (insn))
+ {
+ rn = GET_PUSHED_REG (insn);
+ where[rn] = depth;
+ depth += 4;
+ }
+ else if (IS_STS (insn))
+ {
+ where[tdep->PR_REGNUM] = depth;
+ /* If we're storing the pr then this isn't a leaf */
+ fi->extra_info->leaf_function = 0;
+ depth += 4;
+ }
+ else if (IS_MOV_R3 (insn))
+ {
+ r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
+ }
+ else if (IS_SHLL_R3 (insn))
+ {
+ r3_val <<= 1;
+ }
+ else if (IS_ADD_R3SP (insn))
+ {
+ depth += -r3_val;
+ }
+ else if (IS_ADD_SP (insn))
+ {
+ depth -= ((insn & 0xff) ^ 0x80) - 0x80;
+ }
+ else if (IS_FMOV (insn))
+ {
+ if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
+ {
+ depth += 8;
+ }
+ else
+ {
+ depth += 4;
+ }
+ }
+ else if (IS_MOV_SP_FP (insn))
+ break;
+#if 0 /* This used to just stop when it found an instruction that
+ was not considered part of the prologue. Now, we just
+ keep going looking for likely instructions. */
+ else
+ break;
+#endif
+ }
+
+ /* Now we know how deep things are, we can work out their addresses */
+
+ for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
+ {
+ if (where[rn] >= 0)
+ {
+ if (rn == FP_REGNUM)
+ have_fp = 1;
+
+ fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
+ }
+ else
+ {
+ fi->saved_regs[rn] = 0;
+ }
+ }
+
+ if (have_fp)
+ {
+ fi->saved_regs[SP_REGNUM] =
+ read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
+ }
+ else
+ {
+ fi->saved_regs[SP_REGNUM] = fi->frame - 4;
+ }
+
+ fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
+ /* Work out the return pc - either from the saved pr or the pr
+ value */
+}
+
+/* Initialize the extra info saved in a FRAME */
+static void
+sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
+{
+
+ fi->extra_info = (struct frame_extra_info *)
+ frame_obstack_alloc (sizeof (struct frame_extra_info));
+
+ if (fi->next)
+ fi->pc = FRAME_SAVED_PC (fi->next);
+
+ if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
+ {
+ /* We need to setup fi->frame here because run_stack_dummy gets it wrong
+ by assuming it's always FP. */
+ fi->frame = deprecated_read_register_dummy (fi->pc, fi->frame,
+ SP_REGNUM);
+ fi->extra_info->return_pc = deprecated_read_register_dummy (fi->pc,
+ fi->frame,
+ PC_REGNUM);
+ fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
+ fi->extra_info->leaf_function = 0;
+ return;
+ }
+ else
+ {
+ FRAME_INIT_SAVED_REGS (fi);
+ fi->extra_info->return_pc =
+ sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
+ }
+}
+
+static void
+sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
+{
+ int media_mode = pc_is_isa32 (fi->pc);
+
+ fi->extra_info = (struct frame_extra_info *)
+ frame_obstack_alloc (sizeof (struct frame_extra_info));
+
+ if (fi->next)
+ fi->pc = FRAME_SAVED_PC (fi->next);
+
+ if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
+ {
+ /* We need to setup fi->frame here because run_stack_dummy gets it wrong
+ by assuming it's always FP. */
+ fi->frame = deprecated_read_register_dummy (fi->pc, fi->frame,
+ SP_REGNUM);
+ fi->extra_info->return_pc =
+ deprecated_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
+ fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
+ fi->extra_info->leaf_function = 0;
+ return;
+ }
+ else
+ {
+ FRAME_INIT_SAVED_REGS (fi);
+ fi->extra_info->return_pc =
+ sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
+ }
+}
+
+void
+sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
+ struct frame_info *frame, int regnum,
+ enum lval_type *lval)
+{
+ int media_mode;
+ int live_regnum = regnum;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (!target_has_registers)
+ error ("No registers.");
+
+ /* Normal systems don't optimize out things with register numbers. */
+ if (optimized != NULL)
+ *optimized = 0;
+
+ if (addrp) /* default assumption: not found in memory */
+ *addrp = 0;
+
+ if (raw_buffer)
+ memset (raw_buffer, 0, sizeof (raw_buffer));
+
+ /* We must do this here, before the following while loop changes
+ frame, and makes it NULL. If this is a media register number,
+ but we are in compact mode, it will become the corresponding
+ compact pseudo register. If there is no corresponding compact
+ pseudo-register what do we do?*/
+ media_mode = pc_is_isa32 (frame->pc);
+ live_regnum = translate_insn_rn (regnum, media_mode);
+
+ /* Note: since the current frame's registers could only have been
+ saved by frames INTERIOR TO the current frame, we skip examining
+ the current frame itself: otherwise, we would be getting the
+ previous frame's registers which were saved by the current frame. */
+
+ while (frame && ((frame = frame->next) != NULL))
+ {
+ if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
+ {
+ if (lval) /* found it in a CALL_DUMMY frame */
+ *lval = not_lval;
+ if (raw_buffer)
+ memcpy (raw_buffer,
+ (deprecated_generic_find_dummy_frame (frame->pc, frame->frame)
+ + REGISTER_BYTE (regnum)),
+ REGISTER_RAW_SIZE (regnum));
+ return;
+ }
+
+ FRAME_INIT_SAVED_REGS (frame);
+ if (frame->saved_regs != NULL
+ && frame->saved_regs[regnum] != 0)
+ {
+ if (lval) /* found it saved on the stack */
+ *lval = lval_memory;
+ if (regnum == SP_REGNUM)
+ {
+ if (raw_buffer) /* SP register treated specially */
+ store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
+ frame->saved_regs[regnum]);
+ }
+ else
+ { /* any other register */
+
+ if (addrp)
+ *addrp = frame->saved_regs[regnum];
+ if (raw_buffer)
+ {
+ int size;
+ if (tdep->sh_abi == SH_ABI_32
+ && (live_regnum == FP_REGNUM
+ || live_regnum == tdep->PR_REGNUM))
+ size = 4;
+ else
+ size = REGISTER_RAW_SIZE (live_regnum);
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
+ read_memory (frame->saved_regs[regnum], raw_buffer, size);
+ else
+ read_memory (frame->saved_regs[regnum],
+ raw_buffer
+ + REGISTER_RAW_SIZE (live_regnum)
+ - size,
+ size);
+ }
+ }
+ return;
+ }
+ }
+
+ /* If we get thru the loop to this point, it means the register was
+ not saved in any frame. Return the actual live-register value. */
+
+ if (lval) /* found it in a live register */
+ *lval = lval_register;
+ if (addrp)
+ *addrp = REGISTER_BYTE (live_regnum);
+ if (raw_buffer)
+ deprecated_read_register_gen (live_regnum, raw_buffer);
+}
+
+/* Extract from an array REGBUF containing the (raw) register state
+ the address in which a function should return its structure value,
+ as a CORE_ADDR (or an expression that can be used as one). */
+static CORE_ADDR
+sh_extract_struct_value_address (char *regbuf)
+{
+ return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
+}
+
+static CORE_ADDR
+sh64_extract_struct_value_address (char *regbuf)
+{
+ return (extract_address ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
+ REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM)));
+}
+
+static CORE_ADDR
+sh_frame_saved_pc (struct frame_info *frame)
+{
+ return ((frame)->extra_info->return_pc);
+}
+
+/* Discard from the stack the innermost frame,
+ restoring all saved registers. */
+static void
+sh_pop_frame (void)
+{
+ register struct frame_info *frame = get_current_frame ();
+ register CORE_ADDR fp;
+ register int regnum;
+
+ if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
+ generic_pop_dummy_frame ();
+ else
+ {
+ fp = FRAME_FP (frame);
+ FRAME_INIT_SAVED_REGS (frame);
+
+ /* Copy regs from where they were saved in the frame */
+ for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
+ if (frame->saved_regs[regnum])
+ write_register (regnum,
+ read_memory_integer (frame->saved_regs[regnum], 4));
+
+ write_register (PC_REGNUM, frame->extra_info->return_pc);
+ write_register (SP_REGNUM, fp + 4);
+ }
+ flush_cached_frames ();
+}
+
+/* Used in the 'return' command. */
+static void
+sh64_pop_frame (void)
+{
+ register struct frame_info *frame = get_current_frame ();
+ register CORE_ADDR fp;
+ register int regnum;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ int media_mode = pc_is_isa32 (frame->pc);
+
+ if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
+ generic_pop_dummy_frame ();
+ else
+ {
+ fp = FRAME_FP (frame);
+ FRAME_INIT_SAVED_REGS (frame);
+
+ /* Copy regs from where they were saved in the frame */
+ for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
+ if (frame->saved_regs[regnum])
+ {
+ int size;
+ if (tdep->sh_abi == SH_ABI_32
+ && (regnum == FP_REGNUM
+ || regnum == tdep->PR_REGNUM))
+ size = 4;
+ else
+ size = REGISTER_RAW_SIZE (translate_insn_rn (regnum,
+ media_mode));
+ write_register (regnum,
+ read_memory_integer (frame->saved_regs[regnum],
+ size));
+ }
+
+ write_register (PC_REGNUM, frame->extra_info->return_pc);
+ write_register (SP_REGNUM, fp + 8);
+ }
+ flush_cached_frames ();
+}
+
+/* Function: push_arguments
+ Setup the function arguments for calling a function in the inferior.
+
+ On the Hitachi SH architecture, there are four registers (R4 to R7)
+ which are dedicated for passing function arguments. Up to the first
+ four arguments (depending on size) may go into these registers.
+ The rest go on the stack.
+
+ Arguments that are smaller than 4 bytes will still take up a whole
+ register or a whole 32-bit word on the stack, and will be
+ right-justified in the register or the stack word. This includes
+ chars, shorts, and small aggregate types.
+
+ Arguments that are larger than 4 bytes may be split between two or
+ more registers. If there are not enough registers free, an argument
+ may be passed partly in a register (or registers), and partly on the
+ stack. This includes doubles, long longs, and larger aggregates.
+ As far as I know, there is no upper limit to the size of aggregates
+ that will be passed in this way; in other words, the convention of
+ passing a pointer to a large aggregate instead of a copy is not used.
+
+ An exceptional case exists for struct arguments (and possibly other
+ aggregates such as arrays) if the size is larger than 4 bytes but
+ not a multiple of 4 bytes. In this case the argument is never split
+ between the registers and the stack, but instead is copied in its
+ entirety onto the stack, AND also copied into as many registers as
+ there is room for. In other words, space in registers permitting,
+ two copies of the same argument are passed in. As far as I can tell,
+ only the one on the stack is used, although that may be a function
+ of the level of compiler optimization. I suspect this is a compiler
+ bug. Arguments of these odd sizes are left-justified within the
+ word (as opposed to arguments smaller than 4 bytes, which are
+ right-justified).
+
+ If the function is to return an aggregate type such as a struct, it
+ is either returned in the normal return value register R0 (if its
+ size is no greater than one byte), or else the caller must allocate
+ space into which the callee will copy the return value (if the size
+ is greater than one byte). In this case, a pointer to the return
+ value location is passed into the callee in register R2, which does
+ not displace any of the other arguments passed in via registers R4
+ to R7. */
+
+static CORE_ADDR
+sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
+{
+ int stack_offset, stack_alloc;
+ int argreg;
+ int argnum;
+ struct type *type;
+ CORE_ADDR regval;
+ char *val;
+ char valbuf[4];
+ int len;
+ int odd_sized_struct;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ /* first force sp to a 4-byte alignment */
+ sp = sp & ~3;
+
+ /* The "struct return pointer" pseudo-argument has its own dedicated
+ register */
+ if (struct_return)
+ write_register (STRUCT_RETURN_REGNUM, struct_addr);
+
+ /* Now make sure there's space on the stack */
+ for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
+ stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
+ sp -= stack_alloc; /* make room on stack for args */
+
+ /* Now load as many as possible of the first arguments into
+ registers, and push the rest onto the stack. There are 16 bytes
+ in four registers available. Loop thru args from first to last. */
+
+ argreg = tdep->ARG0_REGNUM;
+ for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
+ {
+ type = VALUE_TYPE (args[argnum]);
+ len = TYPE_LENGTH (type);
+ memset (valbuf, 0, sizeof (valbuf));
+ if (len < 4)
+ {
+ /* value gets right-justified in the register or stack word */
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ memcpy (valbuf + (4 - len),
+ (char *) VALUE_CONTENTS (args[argnum]), len);
+ else
+ memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
+ val = valbuf;
+ }
+ else
+ val = (char *) VALUE_CONTENTS (args[argnum]);
+
+ if (len > 4 && (len & 3) != 0)
+ odd_sized_struct = 1; /* such structs go entirely on stack */
+ else
+ odd_sized_struct = 0;
+ while (len > 0)
+ {
+ if (argreg > tdep->ARGLAST_REGNUM
+ || odd_sized_struct)
+ {
+ /* must go on the stack */
+ write_memory (sp + stack_offset, val, 4);
+ stack_offset += 4;
+ }
+ /* NOTE WELL!!!!! This is not an "else if" clause!!!
+ That's because some *&^%$ things get passed on the stack
+ AND in the registers! */
+ if (argreg <= tdep->ARGLAST_REGNUM)
+ {
+ /* there's room in a register */
+ regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
+ write_register (argreg++, regval);
+ }
+ /* Store the value 4 bytes at a time. This means that things
+ larger than 4 bytes may go partly in registers and partly
+ on the stack. */
+ len -= REGISTER_RAW_SIZE (argreg);
+ val += REGISTER_RAW_SIZE (argreg);
+ }
+ }
+ return sp;
+}
+
+/* R2-R9 for integer types and integer equivalent (char, pointers) and
+ non-scalar (struct, union) elements (even if the elements are
+ floats).
+ FR0-FR11 for single precision floating point (float)
+ DR0-DR10 for double precision floating point (double)
+
+ If a float is argument number 3 (for instance) and arguments number
+ 1,2, and 4 are integer, the mapping will be:
+ arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
+
+ If a float is argument number 10 (for instance) and arguments number
+ 1 through 10 are integer, the mapping will be:
+ arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
+ arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
+ I.e. there is hole in the stack.
+
+ Different rules apply for variable arguments functions, and for functions
+ for which the prototype is not known. */
+
+static CORE_ADDR
+sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
+{
+ int stack_offset, stack_alloc;
+ int int_argreg;
+ int float_argreg;
+ int double_argreg;
+ int float_arg_index = 0;
+ int double_arg_index = 0;
+ int argnum;
+ struct type *type;
+ CORE_ADDR regval;
+ char *val;
+ char valbuf[8];
+ char valbuf_tmp[8];
+ int len;
+ int argreg_size;
+ int fp_args[12];
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ memset (fp_args, 0, sizeof (fp_args));
+
+ /* first force sp to a 8-byte alignment */
+ sp = sp & ~7;
+
+ /* The "struct return pointer" pseudo-argument has its own dedicated
+ register */
+
+ if (struct_return)
+ write_register (STRUCT_RETURN_REGNUM, struct_addr);
+
+ /* Now make sure there's space on the stack */
+ for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
+ stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
+ sp -= stack_alloc; /* make room on stack for args */
+
+ /* Now load as many as possible of the first arguments into
+ registers, and push the rest onto the stack. There are 64 bytes
+ in eight registers available. Loop thru args from first to last. */
+
+ int_argreg = tdep->ARG0_REGNUM;
+ float_argreg = FP0_REGNUM;
+ double_argreg = tdep->DR0_REGNUM;
+
+ for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
+ {
+ type = VALUE_TYPE (args[argnum]);
+ len = TYPE_LENGTH (type);
+ memset (valbuf, 0, sizeof (valbuf));
+
+ if (TYPE_CODE (type) != TYPE_CODE_FLT)
+ {
+ argreg_size = REGISTER_RAW_SIZE (int_argreg);
+
+ if (len < argreg_size)
+ {
+ /* value gets right-justified in the register or stack word */
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ memcpy (valbuf + argreg_size - len,
+ (char *) VALUE_CONTENTS (args[argnum]), len);
+ else
+ memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
+
+ val = valbuf;
+ }
+ else
+ val = (char *) VALUE_CONTENTS (args[argnum]);
+
+ while (len > 0)
+ {
+ if (int_argreg > tdep->ARGLAST_REGNUM)
+ {
+ /* must go on the stack */
+ write_memory (sp + stack_offset, val, argreg_size);
+ stack_offset += 8;/*argreg_size;*/
+ }
+ /* NOTE WELL!!!!! This is not an "else if" clause!!!
+ That's because some *&^%$ things get passed on the stack
+ AND in the registers! */
+ if (int_argreg <= tdep->ARGLAST_REGNUM)
+ {
+ /* there's room in a register */
+ regval = extract_address (val, argreg_size);
+ write_register (int_argreg, regval);
+ }
+ /* Store the value 8 bytes at a time. This means that
+ things larger than 8 bytes may go partly in registers
+ and partly on the stack. FIXME: argreg is incremented
+ before we use its size. */
+ len -= argreg_size;
+ val += argreg_size;
+ int_argreg++;
+ }
+ }
+ else
+ {
+ val = (char *) VALUE_CONTENTS (args[argnum]);
+ if (len == 4)
+ {
+ /* Where is it going to be stored? */
+ while (fp_args[float_arg_index])
+ float_arg_index ++;
+
+ /* Now float_argreg points to the register where it
+ should be stored. Are we still within the allowed
+ register set? */
+ if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM)
+ {
+ /* Goes in FR0...FR11 */
+ deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
+ val);
+ fp_args[float_arg_index] = 1;
+ /* Skip the corresponding general argument register. */
+ int_argreg ++;
+ }
+ else
+ ;
+ /* Store it as the integers, 8 bytes at the time, if
+ necessary spilling on the stack. */
+
+ }
+ else if (len == 8)
+ {
+ /* Where is it going to be stored? */
+ while (fp_args[double_arg_index])
+ double_arg_index += 2;
+ /* Now double_argreg points to the register
+ where it should be stored.
+ Are we still within the allowed register set? */
+ if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM)
+ {
+ /* Goes in DR0...DR10 */
+ /* The numbering of the DRi registers is consecutive,
+ i.e. includes odd numbers. */
+ int double_register_offset = double_arg_index / 2;
+ int regnum = tdep->DR0_REGNUM +
+ double_register_offset;
+#if 0
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
+ {
+ memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
+ REGISTER_CONVERT_TO_VIRTUAL (regnum,
+ type, val, valbuf_tmp);
+ val = valbuf_tmp;
+ }
+#endif
+ /* Note: must use write_register_gen here instead
+ of regcache_raw_write, because
+ regcache_raw_write works only for real
+ registers, not pseudo. write_register_gen will
+ call the gdbarch function to do register
+ writes, and that will properly know how to deal
+ with pseudoregs. */
+ deprecated_write_register_gen (regnum, val);
+ fp_args[double_arg_index] = 1;
+ fp_args[double_arg_index + 1] = 1;
+ /* Skip the corresponding general argument register. */
+ int_argreg ++;
+ }
+ else
+ ;
+ /* Store it as the integers, 8 bytes at the time, if
+ necessary spilling on the stack. */
+ }
+ }
+ }
+ return sp;
+}
+
+/* Function: push_return_address (pc)
+ Set up the return address for the inferior function call.
+ Needed for targets where we don't actually execute a JSR/BSR instruction */
+
+static CORE_ADDR
+sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
+{
+ write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM,
+ CALL_DUMMY_ADDRESS ());
+ return sp;
+}
+
+/* Function: fix_call_dummy
+ Poke the callee function's address into the destination part of
+ the CALL_DUMMY. The address is actually stored in a data word
+ following the actualy CALL_DUMMY instructions, which will load
+ it into a register using PC-relative addressing. This function
+ expects the CALL_DUMMY to look like this:
+
+ mov.w @(2,PC), R8
+ jsr @R8
+ nop
+ trap
+ <destination>
+ */
+
+#if 0
+void
+sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
+ struct value **args, struct type *type, int gcc_p)
+{
+ *(unsigned long *) (dummy + 8) = fun;
+}
+#endif
+
+static int
+sh_coerce_float_to_double (struct type *formal, struct type *actual)
+{
+ return 1;
+}
+
+/* Find a function's return value in the appropriate registers (in
+ regbuf), and copy it into valbuf. Extract from an array REGBUF
+ containing the (raw) register state a function return value of type
+ TYPE, and copy that, in virtual format, into VALBUF. */
+static void
+sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
+{
+ int len = TYPE_LENGTH (type);
+ int return_register = R0_REGNUM;
+ int offset;
+
+ if (len <= 4)
+ {
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ offset = REGISTER_BYTE (return_register) + 4 - len;
+ else
+ offset = REGISTER_BYTE (return_register);
+ memcpy (valbuf, regbuf + offset, len);
+ }
+ else if (len <= 8)
+ {
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ offset = REGISTER_BYTE (return_register) + 8 - len;
+ else
+ offset = REGISTER_BYTE (return_register);
+ memcpy (valbuf, regbuf + offset, len);
+ }
+ else
+ error ("bad size for return value");
+}
+
+static void
+sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf)
+{
+ int return_register;
+ int offset;
+ int len = TYPE_LENGTH (type);
+
+ if (TYPE_CODE (type) == TYPE_CODE_FLT)
+ return_register = FP0_REGNUM;
+ else
+ return_register = R0_REGNUM;
+
+ if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT)
+ {
+ DOUBLEST val;
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
+ floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
+ (char *) regbuf + REGISTER_BYTE (return_register),
+ &val);
+ else
+ floatformat_to_doublest (&floatformat_ieee_double_big,
+ (char *) regbuf + REGISTER_BYTE (return_register),
+ &val);
+ store_floating (valbuf, len, val);
+ }
+ else if (len <= 4)
+ {
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ offset = REGISTER_BYTE (return_register) + 4 - len;
+ else
+ offset = REGISTER_BYTE (return_register);
+ memcpy (valbuf, regbuf + offset, len);
+ }
+ else if (len <= 8)
+ {
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ offset = REGISTER_BYTE (return_register) + 8 - len;
+ else
+ offset = REGISTER_BYTE (return_register);
+ memcpy (valbuf, regbuf + offset, len);
+ }
+ else
+ error ("bad size for return value");
+}
+
+static void
+sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
+{
+ int offset;
+ int return_register;
+ int len = TYPE_LENGTH (type);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (TYPE_CODE (type) == TYPE_CODE_FLT)
+ {
+ if (len == 4)
+ {
+ /* Return value stored in FP0_REGNUM */
+ return_register = FP0_REGNUM;
+ offset = REGISTER_BYTE (return_register);
+ memcpy (valbuf, (char *) regbuf + offset, len);
+ }
+ else if (len == 8)
+ {
+ /* return value stored in DR0_REGNUM */
+ DOUBLEST val;
+
+ return_register = tdep->DR0_REGNUM;
+ offset = REGISTER_BYTE (return_register);
+
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
+ floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
+ (char *) regbuf + offset, &val);
+ else
+ floatformat_to_doublest (&floatformat_ieee_double_big,
+ (char *) regbuf + offset, &val);
+ store_floating (valbuf, len, val);
+ }
+ }
+ else
+ {
+ if (len <= 8)
+ {
+ /* Result is in register 2. If smaller than 8 bytes, it is padded
+ at the most significant end. */
+ return_register = tdep->RETURN_REGNUM;
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ offset = REGISTER_BYTE (return_register) +
+ REGISTER_RAW_SIZE (return_register) - len;
+ else
+ offset = REGISTER_BYTE (return_register);
+ memcpy (valbuf, (char *) regbuf + offset, len);
+ }
+ else
+ error ("bad size for return value");
+ }
+}
+
+/* Write into appropriate registers a function return value
+ of type TYPE, given in virtual format.
+ If the architecture is sh4 or sh3e, store a function's return value
+ in the R0 general register or in the FP0 floating point register,
+ depending on the type of the return value. In all the other cases
+ the result is stored in r0, left-justified. */
+static void
+sh_default_store_return_value (struct type *type, char *valbuf)
+{
+ char buf[32]; /* more than enough... */
+
+ if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM))
+ {
+ /* Add leading zeros to the value. */
+ memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM));
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type),
+ valbuf, TYPE_LENGTH (type));
+ else
+ memcpy (buf, valbuf, TYPE_LENGTH (type));
+ deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf,
+ REGISTER_RAW_SIZE (R0_REGNUM));
+ }
+ else
+ deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf,
+ TYPE_LENGTH (type));
+}
+
+static void
+sh3e_sh4_store_return_value (struct type *type, char *valbuf)
+{
+ if (TYPE_CODE (type) == TYPE_CODE_FLT)
+ deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
+ valbuf, TYPE_LENGTH (type));
+ else
+ sh_default_store_return_value (type, valbuf);
+}
+
+static void
+sh64_store_return_value (struct type *type, char *valbuf)
+{
+ char buf[64]; /* more than enough... */
+ int len = TYPE_LENGTH (type);
+
+ if (TYPE_CODE (type) == TYPE_CODE_FLT)
+ {
+ if (len == 4)
+ {
+ /* Return value stored in FP0_REGNUM */
+ deprecated_write_register_gen (FP0_REGNUM, valbuf);
+ }
+ if (len == 8)
+ {
+ /* return value stored in DR0_REGNUM */
+ /* FIXME: Implement */
+ }
+ }
+ else
+ {
+ int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM;
+ int offset = 0;
+
+ if (len <= REGISTER_RAW_SIZE (return_register))
+ {
+ /* Pad with zeros. */
+ memset (buf, 0, REGISTER_RAW_SIZE (return_register));
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
+ offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
+ else
+ offset = REGISTER_RAW_SIZE (return_register) - len;
+
+ memcpy (buf + offset, valbuf, len);
+ deprecated_write_register_gen (return_register, buf);
+ }
+ else
+ deprecated_write_register_gen (return_register, valbuf);
+ }
+}
+
+/* Print the registers in a form similar to the E7000 */
+
+static void
+sh_generic_show_regs (void)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
+ paddr (read_register (PC_REGNUM)),
+ (long) read_register (tdep->SR_REGNUM),
+ (long) read_register (tdep->PR_REGNUM),
+ (long) read_register (MACH_REGNUM),
+ (long) read_register (MACL_REGNUM));
+
+ printf_filtered ("GBR=%08lx VBR=%08lx",
+ (long) read_register (GBR_REGNUM),
+ (long) read_register (VBR_REGNUM));
+
+ printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0),
+ (long) read_register (1),
+ (long) read_register (2),
+ (long) read_register (3),
+ (long) read_register (4),
+ (long) read_register (5),
+ (long) read_register (6),
+ (long) read_register (7));
+ printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (8),
+ (long) read_register (9),
+ (long) read_register (10),
+ (long) read_register (11),
+ (long) read_register (12),
+ (long) read_register (13),
+ (long) read_register (14),
+ (long) read_register (15));
+}
+
+static void
+sh3_show_regs (void)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
+ paddr (read_register (PC_REGNUM)),
+ (long) read_register (tdep->SR_REGNUM),
+ (long) read_register (tdep->PR_REGNUM),
+ (long) read_register (MACH_REGNUM),
+ (long) read_register (MACL_REGNUM));
+
+ printf_filtered ("GBR=%08lx VBR=%08lx",
+ (long) read_register (GBR_REGNUM),
+ (long) read_register (VBR_REGNUM));
+ printf_filtered (" SSR=%08lx SPC=%08lx",
+ (long) read_register (tdep->SSR_REGNUM),
+ (long) read_register (tdep->SPC_REGNUM));
+
+ printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0),
+ (long) read_register (1),
+ (long) read_register (2),
+ (long) read_register (3),
+ (long) read_register (4),
+ (long) read_register (5),
+ (long) read_register (6),
+ (long) read_register (7));
+ printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (8),
+ (long) read_register (9),
+ (long) read_register (10),
+ (long) read_register (11),
+ (long) read_register (12),
+ (long) read_register (13),
+ (long) read_register (14),
+ (long) read_register (15));
+}
+
+
+static void
+sh3e_show_regs (void)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
+ paddr (read_register (PC_REGNUM)),
+ (long) read_register (tdep->SR_REGNUM),
+ (long) read_register (tdep->PR_REGNUM),
+ (long) read_register (MACH_REGNUM),
+ (long) read_register (MACL_REGNUM));
+
+ printf_filtered ("GBR=%08lx VBR=%08lx",
+ (long) read_register (GBR_REGNUM),
+ (long) read_register (VBR_REGNUM));
+ printf_filtered (" SSR=%08lx SPC=%08lx",
+ (long) read_register (tdep->SSR_REGNUM),
+ (long) read_register (tdep->SPC_REGNUM));
+ printf_filtered (" FPUL=%08lx FPSCR=%08lx",
+ (long) read_register (tdep->FPUL_REGNUM),
+ (long) read_register (tdep->FPSCR_REGNUM));
+
+ printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0),
+ (long) read_register (1),
+ (long) read_register (2),
+ (long) read_register (3),
+ (long) read_register (4),
+ (long) read_register (5),
+ (long) read_register (6),
+ (long) read_register (7));
+ printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (8),
+ (long) read_register (9),
+ (long) read_register (10),
+ (long) read_register (11),
+ (long) read_register (12),
+ (long) read_register (13),
+ (long) read_register (14),
+ (long) read_register (15));
+
+ printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
+ (long) read_register (FP0_REGNUM + 0),
+ (long) read_register (FP0_REGNUM + 1),
+ (long) read_register (FP0_REGNUM + 2),
+ (long) read_register (FP0_REGNUM + 3),
+ (long) read_register (FP0_REGNUM + 4),
+ (long) read_register (FP0_REGNUM + 5),
+ (long) read_register (FP0_REGNUM + 6),
+ (long) read_register (FP0_REGNUM + 7));
+ printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
+ (long) read_register (FP0_REGNUM + 8),
+ (long) read_register (FP0_REGNUM + 9),
+ (long) read_register (FP0_REGNUM + 10),
+ (long) read_register (FP0_REGNUM + 11),
+ (long) read_register (FP0_REGNUM + 12),
+ (long) read_register (FP0_REGNUM + 13),
+ (long) read_register (FP0_REGNUM + 14),
+ (long) read_register (FP0_REGNUM + 15));
+}
+
+static void
+sh3_dsp_show_regs (void)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
+ paddr (read_register (PC_REGNUM)),
+ (long) read_register (tdep->SR_REGNUM),
+ (long) read_register (tdep->PR_REGNUM),
+ (long) read_register (MACH_REGNUM),
+ (long) read_register (MACL_REGNUM));
+
+ printf_filtered ("GBR=%08lx VBR=%08lx",
+ (long) read_register (GBR_REGNUM),
+ (long) read_register (VBR_REGNUM));
+
+ printf_filtered (" SSR=%08lx SPC=%08lx",
+ (long) read_register (tdep->SSR_REGNUM),
+ (long) read_register (tdep->SPC_REGNUM));
+
+ printf_filtered (" DSR=%08lx",
+ (long) read_register (tdep->DSR_REGNUM));
+
+ printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0),
+ (long) read_register (1),
+ (long) read_register (2),
+ (long) read_register (3),
+ (long) read_register (4),
+ (long) read_register (5),
+ (long) read_register (6),
+ (long) read_register (7));
+ printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (8),
+ (long) read_register (9),
+ (long) read_register (10),
+ (long) read_register (11),
+ (long) read_register (12),
+ (long) read_register (13),
+ (long) read_register (14),
+ (long) read_register (15));
+
+ printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
+ (long) read_register (tdep->A0G_REGNUM) & 0xff,
+ (long) read_register (tdep->A0_REGNUM),
+ (long) read_register (tdep->M0_REGNUM),
+ (long) read_register (tdep->X0_REGNUM),
+ (long) read_register (tdep->Y0_REGNUM),
+ (long) read_register (tdep->RS_REGNUM),
+ (long) read_register (tdep->MOD_REGNUM));
+ printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
+ (long) read_register (tdep->A1G_REGNUM) & 0xff,
+ (long) read_register (tdep->A1_REGNUM),
+ (long) read_register (tdep->M1_REGNUM),
+ (long) read_register (tdep->X1_REGNUM),
+ (long) read_register (tdep->Y1_REGNUM),
+ (long) read_register (tdep->RE_REGNUM));
+}
+
+static void
+sh4_show_regs (void)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
+ printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
+ paddr (read_register (PC_REGNUM)),
+ (long) read_register (tdep->SR_REGNUM),
+ (long) read_register (tdep->PR_REGNUM),
+ (long) read_register (MACH_REGNUM),
+ (long) read_register (MACL_REGNUM));
+
+ printf_filtered ("GBR=%08lx VBR=%08lx",
+ (long) read_register (GBR_REGNUM),
+ (long) read_register (VBR_REGNUM));
+ printf_filtered (" SSR=%08lx SPC=%08lx",
+ (long) read_register (tdep->SSR_REGNUM),
+ (long) read_register (tdep->SPC_REGNUM));
+ printf_filtered (" FPUL=%08lx FPSCR=%08lx",
+ (long) read_register (tdep->FPUL_REGNUM),
+ (long) read_register (tdep->FPSCR_REGNUM));
+
+ printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0),
+ (long) read_register (1),
+ (long) read_register (2),
+ (long) read_register (3),
+ (long) read_register (4),
+ (long) read_register (5),
+ (long) read_register (6),
+ (long) read_register (7));
+ printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (8),
+ (long) read_register (9),
+ (long) read_register (10),
+ (long) read_register (11),
+ (long) read_register (12),
+ (long) read_register (13),
+ (long) read_register (14),
+ (long) read_register (15));
+
+ printf_filtered ((pr
+ ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
+ : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
+ (long) read_register (FP0_REGNUM + 0),
+ (long) read_register (FP0_REGNUM + 1),
+ (long) read_register (FP0_REGNUM + 2),
+ (long) read_register (FP0_REGNUM + 3),
+ (long) read_register (FP0_REGNUM + 4),
+ (long) read_register (FP0_REGNUM + 5),
+ (long) read_register (FP0_REGNUM + 6),
+ (long) read_register (FP0_REGNUM + 7));
+ printf_filtered ((pr
+ ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
+ : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
+ (long) read_register (FP0_REGNUM + 8),
+ (long) read_register (FP0_REGNUM + 9),
+ (long) read_register (FP0_REGNUM + 10),
+ (long) read_register (FP0_REGNUM + 11),
+ (long) read_register (FP0_REGNUM + 12),
+ (long) read_register (FP0_REGNUM + 13),
+ (long) read_register (FP0_REGNUM + 14),
+ (long) read_register (FP0_REGNUM + 15));
+}
+
+static void
+sh_dsp_show_regs (void)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
+ paddr (read_register (PC_REGNUM)),
+ (long) read_register (tdep->SR_REGNUM),
+ (long) read_register (tdep->PR_REGNUM),
+ (long) read_register (MACH_REGNUM),
+ (long) read_register (MACL_REGNUM));
+
+ printf_filtered ("GBR=%08lx VBR=%08lx",
+ (long) read_register (GBR_REGNUM),
+ (long) read_register (VBR_REGNUM));
+
+ printf_filtered (" DSR=%08lx",
+ (long) read_register (tdep->DSR_REGNUM));
+
+ printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (0),
+ (long) read_register (1),
+ (long) read_register (2),
+ (long) read_register (3),
+ (long) read_register (4),
+ (long) read_register (5),
+ (long) read_register (6),
+ (long) read_register (7));
+ printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) read_register (8),
+ (long) read_register (9),
+ (long) read_register (10),
+ (long) read_register (11),
+ (long) read_register (12),
+ (long) read_register (13),
+ (long) read_register (14),
+ (long) read_register (15));
+
+ printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
+ (long) read_register (tdep->A0G_REGNUM) & 0xff,
+ (long) read_register (tdep->A0_REGNUM),
+ (long) read_register (tdep->M0_REGNUM),
+ (long) read_register (tdep->X0_REGNUM),
+ (long) read_register (tdep->Y0_REGNUM),
+ (long) read_register (tdep->RS_REGNUM),
+ (long) read_register (tdep->MOD_REGNUM));
+ printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
+ (long) read_register (tdep->A1G_REGNUM) & 0xff,
+ (long) read_register (tdep->A1_REGNUM),
+ (long) read_register (tdep->M1_REGNUM),
+ (long) read_register (tdep->X1_REGNUM),
+ (long) read_register (tdep->Y1_REGNUM),
+ (long) read_register (tdep->RE_REGNUM));
+}
+
+static void
+sh64_show_media_regs (void)
+{
+ int i;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ printf_filtered ("PC=%s SR=%016llx \n",
+ paddr (read_register (PC_REGNUM)),
+ (long long) read_register (tdep->SR_REGNUM));
+
+ printf_filtered ("SSR=%016llx SPC=%016llx \n",
+ (long long) read_register (tdep->SSR_REGNUM),
+ (long long) read_register (tdep->SPC_REGNUM));
+ printf_filtered ("FPSCR=%016lx\n ",
+ (long) read_register (tdep->FPSCR_REGNUM));
+
+ for (i = 0; i < 64; i = i + 4)
+ printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
+ i, i + 3,
+ (long long) read_register (i + 0),
+ (long long) read_register (i + 1),
+ (long long) read_register (i + 2),
+ (long long) read_register (i + 3));
+
+ printf_filtered ("\n");
+
+ for (i = 0; i < 64; i = i + 8)
+ printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ i, i + 7,
+ (long) read_register (FP0_REGNUM + i + 0),
+ (long) read_register (FP0_REGNUM + i + 1),
+ (long) read_register (FP0_REGNUM + i + 2),
+ (long) read_register (FP0_REGNUM + i + 3),
+ (long) read_register (FP0_REGNUM + i + 4),
+ (long) read_register (FP0_REGNUM + i + 5),
+ (long) read_register (FP0_REGNUM + i + 6),
+ (long) read_register (FP0_REGNUM + i + 7));
+}
+
+static void
+sh64_show_compact_regs (void)
+{
+ int i;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ printf_filtered ("PC=%s \n",
+ paddr (read_register (tdep->PC_C_REGNUM)));
+
+ printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
+ (long) read_register (tdep->GBR_C_REGNUM),
+ (long) read_register (tdep->MACH_C_REGNUM),
+ (long) read_register (tdep->MACL_C_REGNUM),
+ (long) read_register (tdep->PR_C_REGNUM),
+ (long) read_register (tdep->T_C_REGNUM));
+ printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
+ (long) read_register (tdep->FPSCR_REGNUM),
+ (long) read_register (tdep->FPUL_REGNUM));
+
+ for (i = 0; i < 16; i = i + 4)
+ printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
+ i, i + 3,
+ (long) read_register (i + 0),
+ (long) read_register (i + 1),
+ (long) read_register (i + 2),
+ (long) read_register (i + 3));
+
+ printf_filtered ("\n");
+
+ for (i = 0; i < 16; i = i + 8)
+ printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ i, i + 7,
+ (long) read_register (FP0_REGNUM + i + 0),
+ (long) read_register (FP0_REGNUM + i + 1),
+ (long) read_register (FP0_REGNUM + i + 2),
+ (long) read_register (FP0_REGNUM + i + 3),
+ (long) read_register (FP0_REGNUM + i + 4),
+ (long) read_register (FP0_REGNUM + i + 5),
+ (long) read_register (FP0_REGNUM + i + 6),
+ (long) read_register (FP0_REGNUM + i + 7));
+}
+
+/*FIXME!!! This only shows the registers for shmedia, excluding the
+ pseudo registers. */
+static void
+sh64_show_regs (void)
+{
+ if (pc_is_isa32 (selected_frame->pc))
+ sh64_show_media_regs ();
+ else
+ sh64_show_compact_regs ();
+}
+
+void sh_show_regs_command (char *args, int from_tty)
+{
+ if (sh_show_regs)
+ (*sh_show_regs)();
+}
+
+/* Index within `registers' of the first byte of the space for
+ register N. */
+static int
+sh_default_register_byte (int reg_nr)
+{
+ return (reg_nr * 4);
+}
+
+static int
+sh_sh4_register_byte (int reg_nr)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (reg_nr >= tdep->DR0_REGNUM
+ && reg_nr <= tdep->DR_LAST_REGNUM)
+ return (dr_reg_base_num (reg_nr) * 4);
+ else if (reg_nr >= tdep->FV0_REGNUM
+ && reg_nr <= tdep->FV_LAST_REGNUM)
+ return (fv_reg_base_num (reg_nr) * 4);
+ else
+ return (reg_nr * 4);
+}
+
+/* *INDENT-OFF* */
+/*
+ SH MEDIA MODE (ISA 32)
+ general registers (64-bit) 0-63
+0 r0, r1, r2, r3, r4, r5, r6, r7,
+64 r8, r9, r10, r11, r12, r13, r14, r15,
+128 r16, r17, r18, r19, r20, r21, r22, r23,
+192 r24, r25, r26, r27, r28, r29, r30, r31,
+256 r32, r33, r34, r35, r36, r37, r38, r39,
+320 r40, r41, r42, r43, r44, r45, r46, r47,
+384 r48, r49, r50, r51, r52, r53, r54, r55,
+448 r56, r57, r58, r59, r60, r61, r62, r63,
+
+ pc (64-bit) 64
+512 pc,
+
+ status reg., saved status reg., saved pc reg. (64-bit) 65-67
+520 sr, ssr, spc,
+
+ target registers (64-bit) 68-75
+544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
+
+ floating point state control register (32-bit) 76
+608 fpscr,
+
+ single precision floating point registers (32-bit) 77-140
+612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
+644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
+676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
+708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
+740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
+772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
+804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
+836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
+
+TOTAL SPACE FOR REGISTERS: 868 bytes
+
+From here on they are all pseudo registers: no memory allocated.
+REGISTER_BYTE returns the register byte for the base register.
+
+ double precision registers (pseudo) 141-172
+ dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
+ dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
+ dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
+ dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
+
+ floating point pairs (pseudo) 173-204
+ fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
+ fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
+ fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
+ fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
+
+ floating point vectors (4 floating point regs) (pseudo) 205-220
+ fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
+ fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
+
+ SH COMPACT MODE (ISA 16) (all pseudo) 221-272
+ r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
+ r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
+ pc_c,
+ gbr_c, mach_c, macl_c, pr_c, t_c,
+ fpscr_c, fpul_c,
+ fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
+ fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
+ dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
+ fv0_c, fv4_c, fv8_c, fv12_c
+*/
+/* *INDENT-ON* */
+static int
+sh_sh64_register_byte (int reg_nr)
+{
+ int base_regnum = -1;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ /* If it is a pseudo register, get the number of the first floating
+ point register that is part of it. */
+ if (reg_nr >= tdep->DR0_REGNUM
+ && reg_nr <= tdep->DR_LAST_REGNUM)
+ base_regnum = dr_reg_base_num (reg_nr);
+
+ else if (reg_nr >= tdep->FPP0_REGNUM
+ && reg_nr <= tdep->FPP_LAST_REGNUM)
+ base_regnum = fpp_reg_base_num (reg_nr);
+
+ else if (reg_nr >= tdep->FV0_REGNUM
+ && reg_nr <= tdep->FV_LAST_REGNUM)
+ base_regnum = fv_reg_base_num (reg_nr);
+
+ /* sh compact pseudo register. FPSCR is a pathological case, need to
+ treat it as special. */
+ else if ((reg_nr >= tdep->R0_C_REGNUM
+ && reg_nr <= tdep->FV_LAST_C_REGNUM)
+ && reg_nr != tdep->FPSCR_C_REGNUM)
+ base_regnum = sh64_compact_reg_base_num (reg_nr);
+
+ /* Now return the offset in bytes within the register cache. */
+ /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
+ if (reg_nr >= tdep->DR0_REGNUM
+ && reg_nr <= tdep->FV_LAST_REGNUM)
+ return (base_regnum - FP0_REGNUM + 1) * 4
+ + (tdep->TR7_REGNUM + 1) * 8;
+
+ /* sh compact pseudo register: general register */
+ if ((reg_nr >= tdep->R0_C_REGNUM
+ && reg_nr <= tdep->R_LAST_C_REGNUM))
+ return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
+ ? base_regnum * 8 + 4
+ : base_regnum * 8);
+
+ /* sh compact pseudo register: */
+ if (reg_nr == tdep->PC_C_REGNUM
+ || reg_nr == tdep->GBR_C_REGNUM
+ || reg_nr == tdep->MACL_C_REGNUM
+ || reg_nr == tdep->PR_C_REGNUM)
+ return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
+ ? base_regnum * 8 + 4
+ : base_regnum * 8);
+
+ if (reg_nr == tdep->MACH_C_REGNUM)
+ return base_regnum * 8;
+
+ if (reg_nr == tdep->T_C_REGNUM)
+ return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
+
+ /* sh compact pseudo register: floating point register */
+ else if (reg_nr >=tdep->FP0_C_REGNUM
+ && reg_nr <= tdep->FV_LAST_C_REGNUM)
+ return (base_regnum - FP0_REGNUM) * 4
+ + (tdep->TR7_REGNUM + 1) * 8 + 4;
+
+ else if (reg_nr == tdep->FPSCR_C_REGNUM)
+ /* This is complicated, for now return the beginning of the
+ architectural FPSCR register. */
+ return (tdep->TR7_REGNUM + 1) * 8;
+
+ else if (reg_nr == tdep->FPUL_C_REGNUM)
+ return ((base_regnum - FP0_REGNUM) * 4 +
+ (tdep->TR7_REGNUM + 1) * 8 + 4);
+
+ /* It is not a pseudo register. */
+ /* It is a 64 bit register. */
+ else if (reg_nr <= tdep->TR7_REGNUM)
+ return reg_nr * 8;
+
+ /* It is a 32 bit register. */
+ else
+ if (reg_nr == tdep->FPSCR_REGNUM)
+ return (tdep->FPSCR_REGNUM * 8);
+
+ /* It is floating point 32-bit register */
+ else
+ return ((tdep->TR7_REGNUM + 1) * 8
+ + (reg_nr - FP0_REGNUM + 1) * 4);
+}
+
+/* Number of bytes of storage in the actual machine representation for
+ register REG_NR. */
+static int
+sh_default_register_raw_size (int reg_nr)
+{
+ return 4;
+}
+
+static int
+sh_sh4_register_raw_size (int reg_nr)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (reg_nr >= tdep->DR0_REGNUM
+ && reg_nr <= tdep->DR_LAST_REGNUM)
+ return 8;
+ else if (reg_nr >= tdep->FV0_REGNUM
+ && reg_nr <= tdep->FV_LAST_REGNUM)
+ return 16;
+ else
+ return 4;
+}
+
+static int
+sh_sh64_register_raw_size (int reg_nr)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if ((reg_nr >= tdep->DR0_REGNUM
+ && reg_nr <= tdep->DR_LAST_REGNUM)
+ || (reg_nr >= tdep->FPP0_REGNUM
+ && reg_nr <= tdep->FPP_LAST_REGNUM)
+ || (reg_nr >= tdep->DR0_C_REGNUM
+ && reg_nr <= tdep->DR_LAST_C_REGNUM)
+ || (reg_nr <= tdep->TR7_REGNUM))
+ return 8;
+
+ else if ((reg_nr >= tdep->FV0_REGNUM
+ && reg_nr <= tdep->FV_LAST_REGNUM)
+ || (reg_nr >= tdep->FV0_C_REGNUM
+ && reg_nr <= tdep->FV_LAST_C_REGNUM))
+ return 16;
+
+ else /* this covers also the 32-bit SH compact registers. */
+ return 4;
+}
+
+/* Number of bytes of storage in the program's representation
+ for register N. */
+static int
+sh_register_virtual_size (int reg_nr)
+{
+ return 4;
+}
+
+/* ??????? FIXME */
+static int
+sh_sh64_register_virtual_size (int reg_nr)
+{
+ if (reg_nr >= FP0_REGNUM
+ && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM)
+ return 4;
+ else
+ return 8;
+}
+
+/* Return the GDB type object for the "standard" data type
+ of data in register N. */
+static struct type *
+sh_sh3e_register_virtual_type (int reg_nr)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if ((reg_nr >= FP0_REGNUM
+ && (reg_nr <= tdep->FP_LAST_REGNUM))
+ || (reg_nr == tdep->FPUL_REGNUM))
+ return builtin_type_float;
+ else
+ return builtin_type_int;
+}
+
+static struct type *
+sh_sh4_build_float_register_type (int high)
+{
+ struct type *temp;
+
+ temp = create_range_type (NULL, builtin_type_int, 0, high);
+ return create_array_type (NULL, builtin_type_float, temp);
+}
+
+static struct type *
+sh_sh4_register_virtual_type (int reg_nr)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if ((reg_nr >= FP0_REGNUM
+ && (reg_nr <= tdep->FP_LAST_REGNUM))
+ || (reg_nr == tdep->FPUL_REGNUM))
+ return builtin_type_float;
+ else if (reg_nr >= tdep->DR0_REGNUM
+ && reg_nr <= tdep->DR_LAST_REGNUM)
+ return builtin_type_double;
+ else if (reg_nr >= tdep->FV0_REGNUM
+ && reg_nr <= tdep->FV_LAST_REGNUM)
+ return sh_sh4_build_float_register_type (3);
+ else
+ return builtin_type_int;
+}
+
+static struct type *
+sh_sh64_register_virtual_type (int reg_nr)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if ((reg_nr >= FP0_REGNUM
+ && reg_nr <= tdep->FP_LAST_REGNUM)
+ || (reg_nr >= tdep->FP0_C_REGNUM
+ && reg_nr <= tdep->FP_LAST_C_REGNUM))
+ return builtin_type_float;
+ else if ((reg_nr >= tdep->DR0_REGNUM
+ && reg_nr <= tdep->DR_LAST_REGNUM)
+ || (reg_nr >= tdep->DR0_C_REGNUM
+ && reg_nr <= tdep->DR_LAST_C_REGNUM))
+ return builtin_type_double;
+ else if (reg_nr >= tdep->FPP0_REGNUM
+ && reg_nr <= tdep->FPP_LAST_REGNUM)
+ return sh_sh4_build_float_register_type (1);
+ else if ((reg_nr >= tdep->FV0_REGNUM
+ && reg_nr <= tdep->FV_LAST_REGNUM)
+ ||(reg_nr >= tdep->FV0_C_REGNUM
+ && reg_nr <= tdep->FV_LAST_C_REGNUM))
+ return sh_sh4_build_float_register_type (3);
+ else if (reg_nr == tdep->FPSCR_REGNUM)
+ return builtin_type_int;
+ else if (reg_nr >= tdep->R0_C_REGNUM
+ && reg_nr < tdep->FP0_C_REGNUM)
+ return builtin_type_int;
+ else
+ return builtin_type_long_long;
+}
+
+static struct type *
+sh_default_register_virtual_type (int reg_nr)
+{
+ return builtin_type_int;
+}
+
+/* On the sh4, the DRi pseudo registers are problematic if the target
+ is little endian. When the user writes one of those registers, for
+ instance with 'ser var $dr0=1', we want the double to be stored
+ like this:
+ fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
+ fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+
+ This corresponds to little endian byte order & big endian word
+ order. However if we let gdb write the register w/o conversion, it
+ will write fr0 and fr1 this way:
+ fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
+ because it will consider fr0 and fr1 as a single LE stretch of memory.
+
+ To achieve what we want we must force gdb to store things in
+ floatformat_ieee_double_littlebyte_bigword (which is defined in
+ include/floatformat.h and libiberty/floatformat.c.
+
+ In case the target is big endian, there is no problem, the
+ raw bytes will look like:
+ fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
+ fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+
+ The other pseudo registers (the FVs) also don't pose a problem
+ because they are stored as 4 individual FP elements. */
+
+static void
+sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
+ char *from, char *to)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (regnum >= tdep->DR0_REGNUM
+ && regnum <= tdep->DR_LAST_REGNUM)
+ {
+ DOUBLEST val;
+ floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
+ store_floating (to, TYPE_LENGTH (type), val);
+ }
+ else
+ error ("sh_register_convert_to_virtual called with non DR register number");
+}
+
+void
+sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
+ char *from, char *to)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
+ {
+ /* It is a no-op. */
+ memcpy (to, from, REGISTER_RAW_SIZE (regnum));
+ return;
+ }
+
+ if ((regnum >= tdep->DR0_REGNUM
+ && regnum <= tdep->DR_LAST_REGNUM)
+ || (regnum >= tdep->DR0_C_REGNUM
+ && regnum <= tdep->DR_LAST_C_REGNUM))
+ {
+ DOUBLEST val;
+ floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
+ store_floating(to, TYPE_LENGTH(type), val);
+ }
+ else
+ error("sh_register_convert_to_virtual called with non DR register number");
+}
+
+static void
+sh_sh4_register_convert_to_raw (struct type *type, int regnum,
+ const void *from, void *to)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (regnum >= tdep->DR0_REGNUM
+ && regnum <= tdep->DR_LAST_REGNUM)
+ {
+ DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
+ floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
+ }
+ else
+ error("sh_register_convert_to_raw called with non DR register number");
+}
+
+void
+sh_sh64_register_convert_to_raw (struct type *type, int regnum,
+ const void *from, void *to)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
+ {
+ /* It is a no-op. */
+ memcpy (to, from, REGISTER_RAW_SIZE (regnum));
+ return;
+ }
+
+ if ((regnum >= tdep->DR0_REGNUM
+ && regnum <= tdep->DR_LAST_REGNUM)
+ || (regnum >= tdep->DR0_C_REGNUM
+ && regnum <= tdep->DR_LAST_C_REGNUM))
+ {
+ DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
+ floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
+ }
+ else
+ error("sh_register_convert_to_raw called with non DR register number");
+}
+
+void
+sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
+ int reg_nr, void *buffer)
+{
+ int base_regnum, portion;
+ char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (reg_nr >= tdep->DR0_REGNUM
+ && reg_nr <= tdep->DR_LAST_REGNUM)
+ {
+ base_regnum = dr_reg_base_num (reg_nr);
+
+ /* Build the value in the provided buffer. */
+ /* Read the real regs for which this one is an alias. */
+ for (portion = 0; portion < 2; portion++)
+ regcache_raw_read (regcache, base_regnum + portion,
+ (temp_buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+ /* We must pay attention to the endiannes. */
+ sh_sh4_register_convert_to_virtual (reg_nr,
+ REGISTER_VIRTUAL_TYPE (reg_nr),
+ temp_buffer, buffer);
+ }
+ else if (reg_nr >= tdep->FV0_REGNUM
+ && reg_nr <= tdep->FV_LAST_REGNUM)
+ {
+ base_regnum = fv_reg_base_num (reg_nr);
+
+ /* Read the real regs for which this one is an alias. */
+ for (portion = 0; portion < 4; portion++)
+ regcache_raw_read (regcache, base_regnum + portion,
+ ((char *) buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+ }
+}
+
+static void
+sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
+ int reg_nr, void *buffer)
+{
+ int base_regnum;
+ int portion;
+ int offset = 0;
+ char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (reg_nr >= tdep->DR0_REGNUM
+ && reg_nr <= tdep->DR_LAST_REGNUM)
+ {
+ base_regnum = dr_reg_base_num (reg_nr);
+
+ /* Build the value in the provided buffer. */
+ /* DR regs are double precision registers obtained by
+ concatenating 2 single precision floating point registers. */
+ for (portion = 0; portion < 2; portion++)
+ regcache_raw_read (regcache, base_regnum + portion,
+ (temp_buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+
+ /* We must pay attention to the endiannes. */
+ sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
+ temp_buffer, buffer);
+
+ }
+
+ else if (reg_nr >= tdep->FPP0_REGNUM
+ && reg_nr <= tdep->FPP_LAST_REGNUM)
+ {
+ base_regnum = fpp_reg_base_num (reg_nr);
+
+ /* Build the value in the provided buffer. */
+ /* FPP regs are pairs of single precision registers obtained by
+ concatenating 2 single precision floating point registers. */
+ for (portion = 0; portion < 2; portion++)
+ regcache_raw_read (regcache, base_regnum + portion,
+ ((char *) buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+ }
+
+ else if (reg_nr >= tdep->FV0_REGNUM
+ && reg_nr <= tdep->FV_LAST_REGNUM)
+ {
+ base_regnum = fv_reg_base_num (reg_nr);
+
+ /* Build the value in the provided buffer. */
+ /* FV regs are vectors of single precision registers obtained by
+ concatenating 4 single precision floating point registers. */
+ for (portion = 0; portion < 4; portion++)
+ regcache_raw_read (regcache, base_regnum + portion,
+ ((char *) buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+ }
+
+ /* sh compact pseudo registers. 1-to-1 with a shmedia register */
+ else if (reg_nr >= tdep->R0_C_REGNUM
+ && reg_nr <= tdep->T_C_REGNUM)
+ {
+ base_regnum = sh64_compact_reg_base_num (reg_nr);
+
+ /* Build the value in the provided buffer. */
+ regcache_raw_read (regcache, base_regnum, temp_buffer);
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ offset = 4;
+ memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
+ }
+
+ else if (reg_nr >= tdep->FP0_C_REGNUM
+ && reg_nr <= tdep->FP_LAST_C_REGNUM)
+ {
+ base_regnum = sh64_compact_reg_base_num (reg_nr);
+
+ /* Build the value in the provided buffer. */
+ /* Floating point registers map 1-1 to the media fp regs,
+ they have the same size and endienness. */
+ regcache_raw_read (regcache, base_regnum, buffer);
+ }
+
+ else if (reg_nr >= tdep->DR0_C_REGNUM
+ && reg_nr <= tdep->DR_LAST_C_REGNUM)
+ {
+ base_regnum = sh64_compact_reg_base_num (reg_nr);
+
+ /* DR_C regs are double precision registers obtained by
+ concatenating 2 single precision floating point registers. */
+ for (portion = 0; portion < 2; portion++)
+ regcache_raw_read (regcache, base_regnum + portion,
+ (temp_buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+
+ /* We must pay attention to the endiannes. */
+ sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
+ temp_buffer, buffer);
+ }
+
+ else if (reg_nr >= tdep->FV0_C_REGNUM
+ && reg_nr <= tdep->FV_LAST_C_REGNUM)
+ {
+ base_regnum = sh64_compact_reg_base_num (reg_nr);
+
+ /* Build the value in the provided buffer. */
+ /* FV_C regs are vectors of single precision registers obtained by
+ concatenating 4 single precision floating point registers. */
+ for (portion = 0; portion < 4; portion++)
+ regcache_raw_read (regcache, base_regnum + portion,
+ ((char *) buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+ }
+
+ else if (reg_nr == tdep->FPSCR_C_REGNUM)
+ {
+ int fpscr_base_regnum;
+ int sr_base_regnum;
+ unsigned int fpscr_value;
+ unsigned int sr_value;
+ unsigned int fpscr_c_value;
+ unsigned int fpscr_c_part1_value;
+ unsigned int fpscr_c_part2_value;
+
+ fpscr_base_regnum = tdep->FPSCR_REGNUM;
+ sr_base_regnum = tdep->SR_REGNUM;
+
+ /* Build the value in the provided buffer. */
+ /* FPSCR_C is a very weird register that contains sparse bits
+ from the FPSCR and the SR architectural registers.
+ Specifically: */
+ /* *INDENT-OFF* */
+ /*
+ FPSRC_C bit
+ 0 Bit 0 of FPSCR
+ 1 reserved
+ 2-17 Bit 2-18 of FPSCR
+ 18-20 Bits 12,13,14 of SR
+ 21-31 reserved
+ */
+ /* *INDENT-ON* */
+ /* Get FPSCR into a local buffer */
+ regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
+ /* Get value as an int. */
+ fpscr_value = extract_unsigned_integer (temp_buffer, 4);
+ /* Get SR into a local buffer */
+ regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
+ /* Get value as an int. */
+ sr_value = extract_unsigned_integer (temp_buffer, 4);
+ /* Build the new value. */
+ fpscr_c_part1_value = fpscr_value & 0x3fffd;
+ fpscr_c_part2_value = (sr_value & 0x7000) << 6;
+ fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
+ /* Store that in out buffer!!! */
+ store_unsigned_integer (buffer, 4, fpscr_c_value);
+ /* FIXME There is surely an endianness gotcha here. */
+ }
+
+ else if (reg_nr == tdep->FPUL_C_REGNUM)
+ {
+ base_regnum = sh64_compact_reg_base_num (reg_nr);
+
+ /* FPUL_C register is floating point register 32,
+ same size, same endianness. */
+ regcache_raw_read (regcache, base_regnum, buffer);
+ }
+}
+
+void
+sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
+ int reg_nr, const void *buffer)
+{
+ int base_regnum, portion;
+ char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (reg_nr >= tdep->DR0_REGNUM
+ && reg_nr <= tdep->DR_LAST_REGNUM)
+ {
+ base_regnum = dr_reg_base_num (reg_nr);
+
+ /* We must pay attention to the endiannes. */
+ sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
+ buffer, temp_buffer);
+
+ /* Write the real regs for which this one is an alias. */
+ for (portion = 0; portion < 2; portion++)
+ regcache_raw_write (regcache, base_regnum + portion,
+ (temp_buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+ }
+ else if (reg_nr >= tdep->FV0_REGNUM
+ && reg_nr <= tdep->FV_LAST_REGNUM)
+ {
+ base_regnum = fv_reg_base_num (reg_nr);
+
+ /* Write the real regs for which this one is an alias. */
+ for (portion = 0; portion < 4; portion++)
+ regcache_raw_write (regcache, base_regnum + portion,
+ ((char *) buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+ }
+}
+
+void
+sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
+ int reg_nr, const void *buffer)
+{
+ int base_regnum, portion;
+ int offset;
+ char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (reg_nr >= tdep->DR0_REGNUM
+ && reg_nr <= tdep->DR_LAST_REGNUM)
+ {
+ base_regnum = dr_reg_base_num (reg_nr);
+ /* We must pay attention to the endiannes. */
+ sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
+ buffer, temp_buffer);
+
+
+ /* Write the real regs for which this one is an alias. */
+ for (portion = 0; portion < 2; portion++)
+ regcache_raw_write (regcache, base_regnum + portion,
+ (temp_buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+ }
+
+ else if (reg_nr >= tdep->FPP0_REGNUM
+ && reg_nr <= tdep->FPP_LAST_REGNUM)
+ {
+ base_regnum = fpp_reg_base_num (reg_nr);
+
+ /* Write the real regs for which this one is an alias. */
+ for (portion = 0; portion < 2; portion++)
+ regcache_raw_write (regcache, base_regnum + portion,
+ ((char *) buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+ }
+
+ else if (reg_nr >= tdep->FV0_REGNUM
+ && reg_nr <= tdep->FV_LAST_REGNUM)
+ {
+ base_regnum = fv_reg_base_num (reg_nr);
+
+ /* Write the real regs for which this one is an alias. */
+ for (portion = 0; portion < 4; portion++)
+ regcache_raw_write (regcache, base_regnum + portion,
+ ((char *) buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+ }
+
+ /* sh compact general pseudo registers. 1-to-1 with a shmedia
+ register but only 4 bytes of it. */
+ else if (reg_nr >= tdep->R0_C_REGNUM
+ && reg_nr <= tdep->T_C_REGNUM)
+ {
+ base_regnum = sh64_compact_reg_base_num (reg_nr);
+ /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ offset = 4;
+ else
+ offset = 0;
+ /* Let's read the value of the base register into a temporary
+ buffer, so that overwriting the last four bytes with the new
+ value of the pseudo will leave the upper 4 bytes unchanged. */
+ regcache_raw_read (regcache, base_regnum, temp_buffer);
+ /* Write as an 8 byte quantity */
+ memcpy (temp_buffer + offset, buffer, 4);
+ regcache_raw_write (regcache, base_regnum, temp_buffer);
+ }
+
+ /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
+ registers. Both are 4 bytes. */
+ else if (reg_nr >= tdep->FP0_C_REGNUM
+ && reg_nr <= tdep->FP_LAST_C_REGNUM)
+ {
+ base_regnum = sh64_compact_reg_base_num (reg_nr);
+ regcache_raw_write (regcache, base_regnum, buffer);
+ }
+
+ else if (reg_nr >= tdep->DR0_C_REGNUM
+ && reg_nr <= tdep->DR_LAST_C_REGNUM)
+ {
+ base_regnum = sh64_compact_reg_base_num (reg_nr);
+ for (portion = 0; portion < 2; portion++)
+ {
+ /* We must pay attention to the endiannes. */
+ sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
+ buffer, temp_buffer);
+
+ regcache_raw_write (regcache, base_regnum + portion,
+ (temp_buffer
+ + REGISTER_RAW_SIZE (base_regnum) * portion));
+ }
+ }
+
+ else if (reg_nr >= tdep->FV0_C_REGNUM
+ && reg_nr <= tdep->FV_LAST_C_REGNUM)
+ {
+ base_regnum = sh64_compact_reg_base_num (reg_nr);
+
+ for (portion = 0; portion < 4; portion++)