-/* Index within `registers' of the first byte of the space for
- register N. */
-static int
-sh_default_register_byte (int reg_nr)
-{
- return (reg_nr * 4);
-}
-
-static int
-sh_sh4_register_byte (int reg_nr)
-{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-
- if (reg_nr >= tdep->DR0_REGNUM
- && reg_nr <= tdep->DR_LAST_REGNUM)
- return (dr_reg_base_num (reg_nr) * 4);
- else if (reg_nr >= tdep->FV0_REGNUM
- && reg_nr <= tdep->FV_LAST_REGNUM)
- return (fv_reg_base_num (reg_nr) * 4);
- else
- return (reg_nr * 4);
-}
-
-/* *INDENT-OFF* */
-/*
- SH MEDIA MODE (ISA 32)
- general registers (64-bit) 0-63
-0 r0, r1, r2, r3, r4, r5, r6, r7,
-64 r8, r9, r10, r11, r12, r13, r14, r15,
-128 r16, r17, r18, r19, r20, r21, r22, r23,
-192 r24, r25, r26, r27, r28, r29, r30, r31,
-256 r32, r33, r34, r35, r36, r37, r38, r39,
-320 r40, r41, r42, r43, r44, r45, r46, r47,
-384 r48, r49, r50, r51, r52, r53, r54, r55,
-448 r56, r57, r58, r59, r60, r61, r62, r63,
-
- pc (64-bit) 64
-512 pc,
-
- status reg., saved status reg., saved pc reg. (64-bit) 65-67
-520 sr, ssr, spc,
-
- target registers (64-bit) 68-75
-544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
-
- floating point state control register (32-bit) 76
-608 fpscr,
-
- single precision floating point registers (32-bit) 77-140
-612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
-644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
-676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
-708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
-740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
-772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
-804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
-836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
-
-TOTAL SPACE FOR REGISTERS: 868 bytes
-
-From here on they are all pseudo registers: no memory allocated.
-REGISTER_BYTE returns the register byte for the base register.
-
- double precision registers (pseudo) 141-172
- dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
- dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
- dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
- dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
-
- floating point pairs (pseudo) 173-204
- fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
- fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
- fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
- fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
-
- floating point vectors (4 floating point regs) (pseudo) 205-220
- fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
- fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
-
- SH COMPACT MODE (ISA 16) (all pseudo) 221-272
- r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
- r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
- pc_c,
- gbr_c, mach_c, macl_c, pr_c, t_c,
- fpscr_c, fpul_c,
- fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
- fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
- dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
- fv0_c, fv4_c, fv8_c, fv12_c
-*/
-/* *INDENT-ON* */
-static int
-sh_sh64_register_byte (int reg_nr)
-{
- int base_regnum = -1;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-
- /* If it is a pseudo register, get the number of the first floating
- point register that is part of it. */
- if (reg_nr >= tdep->DR0_REGNUM
- && reg_nr <= tdep->DR_LAST_REGNUM)
- base_regnum = dr_reg_base_num (reg_nr);
-
- else if (reg_nr >= tdep->FPP0_REGNUM
- && reg_nr <= tdep->FPP_LAST_REGNUM)
- base_regnum = fpp_reg_base_num (reg_nr);
-
- else if (reg_nr >= tdep->FV0_REGNUM
- && reg_nr <= tdep->FV_LAST_REGNUM)
- base_regnum = fv_reg_base_num (reg_nr);
-
- /* sh compact pseudo register. FPSCR is a pathological case, need to
- treat it as special. */
- else if ((reg_nr >= tdep->R0_C_REGNUM
- && reg_nr <= tdep->FV_LAST_C_REGNUM)
- && reg_nr != tdep->FPSCR_C_REGNUM)
- base_regnum = sh64_compact_reg_base_num (reg_nr);
-
- /* Now return the offset in bytes within the register cache. */
- /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
- if (reg_nr >= tdep->DR0_REGNUM
- && reg_nr <= tdep->FV_LAST_REGNUM)
- return (base_regnum - FP0_REGNUM + 1) * 4
- + (tdep->TR7_REGNUM + 1) * 8;
-
- /* sh compact pseudo register: general register */
- if ((reg_nr >= tdep->R0_C_REGNUM
- && reg_nr <= tdep->R_LAST_C_REGNUM))
- return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
- ? base_regnum * 8 + 4
- : base_regnum * 8);
-
- /* sh compact pseudo register: */
- if (reg_nr == tdep->PC_C_REGNUM
- || reg_nr == tdep->GBR_C_REGNUM
- || reg_nr == tdep->MACL_C_REGNUM
- || reg_nr == tdep->PR_C_REGNUM)
- return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
- ? base_regnum * 8 + 4
- : base_regnum * 8);
-
- if (reg_nr == tdep->MACH_C_REGNUM)
- return base_regnum * 8;
-
- if (reg_nr == tdep->T_C_REGNUM)
- return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
-
- /* sh compact pseudo register: floating point register */
- else if (reg_nr >=tdep->FP0_C_REGNUM
- && reg_nr <= tdep->FV_LAST_C_REGNUM)
- return (base_regnum - FP0_REGNUM) * 4
- + (tdep->TR7_REGNUM + 1) * 8 + 4;
-
- else if (reg_nr == tdep->FPSCR_C_REGNUM)
- /* This is complicated, for now return the beginning of the
- architectural FPSCR register. */
- return (tdep->TR7_REGNUM + 1) * 8;
-
- else if (reg_nr == tdep->FPUL_C_REGNUM)
- return ((base_regnum - FP0_REGNUM) * 4 +
- (tdep->TR7_REGNUM + 1) * 8 + 4);
-
- /* It is not a pseudo register. */
- /* It is a 64 bit register. */
- else if (reg_nr <= tdep->TR7_REGNUM)
- return reg_nr * 8;
-
- /* It is a 32 bit register. */
- else
- if (reg_nr == tdep->FPSCR_REGNUM)
- return (tdep->FPSCR_REGNUM * 8);
-
- /* It is floating point 32-bit register */
- else
- return ((tdep->TR7_REGNUM + 1) * 8
- + (reg_nr - FP0_REGNUM + 1) * 4);
-}
-
-/* Number of bytes of storage in the actual machine representation for
- register REG_NR. */
-static int
-sh_default_register_raw_size (int reg_nr)
-{
- return 4;
-}
-
-static int
-sh_sh4_register_raw_size (int reg_nr)
-{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-
- if (reg_nr >= tdep->DR0_REGNUM
- && reg_nr <= tdep->DR_LAST_REGNUM)
- return 8;
- else if (reg_nr >= tdep->FV0_REGNUM
- && reg_nr <= tdep->FV_LAST_REGNUM)
- return 16;
- else
- return 4;
+static void
+sh4_nofpu_show_regs (struct frame_info *frame)
+{
+ printf_filtered
+ (" PC %s SR %08lx PR %08lx MACH %08lx\n",
+ paddr (get_frame_register_unsigned (frame,
+ gdbarch_pc_regnum
+ (get_frame_arch (frame)))),
+ (long) get_frame_register_unsigned (frame, SR_REGNUM),
+ (long) get_frame_register_unsigned (frame, PR_REGNUM),
+ (long) get_frame_register_unsigned (frame, MACH_REGNUM));
+
+ printf_filtered
+ (" GBR %08lx VBR %08lx MACL %08lx\n",
+ (long) get_frame_register_unsigned (frame, GBR_REGNUM),
+ (long) get_frame_register_unsigned (frame, VBR_REGNUM),
+ (long) get_frame_register_unsigned (frame, MACL_REGNUM));
+ printf_filtered
+ (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
+ (long) get_frame_register_unsigned (frame, SSR_REGNUM),
+ (long) get_frame_register_unsigned (frame, SPC_REGNUM),
+ (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
+ (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
+
+ printf_filtered
+ ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) get_frame_register_unsigned (frame, 0),
+ (long) get_frame_register_unsigned (frame, 1),
+ (long) get_frame_register_unsigned (frame, 2),
+ (long) get_frame_register_unsigned (frame, 3),
+ (long) get_frame_register_unsigned (frame, 4),
+ (long) get_frame_register_unsigned (frame, 5),
+ (long) get_frame_register_unsigned (frame, 6),
+ (long) get_frame_register_unsigned (frame, 7));
+ printf_filtered
+ ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+ (long) get_frame_register_unsigned (frame, 8),
+ (long) get_frame_register_unsigned (frame, 9),
+ (long) get_frame_register_unsigned (frame, 10),
+ (long) get_frame_register_unsigned (frame, 11),
+ (long) get_frame_register_unsigned (frame, 12),
+ (long) get_frame_register_unsigned (frame, 13),
+ (long) get_frame_register_unsigned (frame, 14),
+ (long) get_frame_register_unsigned (frame, 15));