- {
- /* 16-bit general purpose registers. */
- r0, r1, r2, r3,
- r4, r5, r6, r7,
- r8, r9, r10, r11,
- r12_L = 12, r13_L = 13, ra = 14, sp_L = 15,
-
- /* 32-bit general purpose registers. */
- r12 = 12, r13 = 13, r14 = 14, r15 = 15,
- era = 14, sp = 15, RA,
-
- /* Not a register. */
- nullregister,
- MAX_REG
- }
+{
+ /* 16-bit general purpose registers. */
+ r0, r1, r2, r3,
+ r4, r5, r6, r7,
+ r8, r9, r10, r11,
+ r12_L = 12, r13_L = 13, ra = 14, sp_L = 15,
+
+ /* 32-bit general purpose registers. */
+ r12 = 12, r13 = 13, r14 = 14, r15 = 15,
+ era = 14, sp = 15, RA,
+
+ /* Not a register. */
+ nullregister,
+ MAX_REG
+}
- {
- /* processor registers. */
- dbs = MAX_REG,
- dsr, dcrl, dcrh,
- car0l, car0h, car1l, car1h,
- cfg, psr, intbasel, intbaseh,
- ispl, isph, uspl, usph,
- dcr = dcrl,
- car0 = car0l,
- car1 = car1l,
- intbase = intbasel,
- isp = ispl,
- usp = uspl,
- /* Not a processor register. */
- nullpregister = usph + 1,
- MAX_PREG
- }
+{
+ /* processor registers. */
+ dbs = MAX_REG,
+ dsr, dcrl, dcrh,
+ car0l, car0h, car1l, car1h,
+ cfg, psr, intbasel, intbaseh,
+ ispl, isph, uspl, usph,
+ dcr = dcrl,
+ car0 = car0l,
+ car1 = car1l,
+ intbase = intbasel,
+ isp = ispl,
+ usp = uspl,
+ /* Not a processor register. */
+ nullpregister = usph + 1,
+ MAX_PREG
+}
- {
- dummy,
- /* N-bit signed immediate. */
- imm3, imm4, imm5, imm6, imm16, imm20, imm32,
- /* N-bit unsigned immediate. */
- uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32,
- /* N-bit signed displacement. */
- disps5, disps17, disps25,
- /* N-bit unsigned displacement. */
- dispe9,
- /* N-bit absolute address. */
- abs20, abs24,
- /* Register relative. */
- rra, rbase, rbase_disps20, rbase_dispe20,
- /* Register pair relative. */
- rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16,
- rpbase_disps20, rpbase_dispe20,
- /* Register index. */
- rindex7_abs20, rindex8_abs20,
- /* Register pair index. */
- rpindex_disps0, rpindex_disps14, rpindex_disps20,
- /* register. */
- regr,
- /* register pair. */
- regp,
- /* processor register. */
- pregr,
- /* processor register 32 bit. */
- pregrp,
- /* condition code - 4 bit. */
- cc,
- /* Not an operand. */
- nulloperand,
- /* Maximum supported operand. */
- MAX_OPRD
- }
+{
+ dummy,
+ /* N-bit signed immediate. */
+ imm3, imm4, imm5, imm6, imm16, imm20, imm32,
+ /* N-bit unsigned immediate. */
+ uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32,
+ /* N-bit signed displacement. */
+ disps5, disps17, disps25,
+ /* N-bit unsigned displacement. */
+ dispe9,
+ /* N-bit absolute address. */
+ abs20, abs24,
+ /* Register relative. */
+ rra, rbase, rbase_disps20, rbase_dispe20,
+ /* Register pair relative. */
+ rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16,
+ rpbase_disps20, rpbase_dispe20,
+ /* Register index. */
+ rindex7_abs20, rindex8_abs20,
+ /* Register pair index. */
+ rpindex_disps0, rpindex_disps14, rpindex_disps20,
+ /* register. */
+ regr,
+ /* register pair. */
+ regp,
+ /* processor register. */
+ pregr,
+ /* processor register 32 bit. */
+ pregrp,
+ /* condition code - 4 bit. */
+ cc,
+ /* Not an operand. */
+ nulloperand,
+ /* Maximum supported operand. */
+ MAX_OPRD
+}
- {
- /* Name. */
- const char *mnemonic;
- /* Size (in words). */
- unsigned int size;
- /* Constant prefix (matched by the disassembler). */
- unsigned long match; /* ie opcode */
- /* Match size (in bits). */
- /* MASK: if( (i & match_bits) == match ) then match */
- int match_bits;
- /* Attributes. */
- unsigned int flags;
- /* Operands (always last, so unreferenced operands are initialized). */
- operand_desc operands[MAX_OPERANDS];
- }
+{
+ /* Name. */
+ const char *mnemonic;
+ /* Size (in words). */
+ unsigned int size;
+ /* Constant prefix (matched by the disassembler). */
+ unsigned long match; /* ie opcode */
+ /* Match size (in bits). */
+ /* MASK: if( (i & match_bits) == match ) then match */
+ int match_bits;
+ /* Attributes. */
+ unsigned int flags;
+ /* Operands (always last, so unreferenced operands are initialized). */
+ operand_desc operands[MAX_OPERANDS];
+}
- {
- /* Register or base register. */
- reg r;
- /* Register pair register. */
- reg rp;
- /* Index register. */
- reg i_r;
- /* Processor register. */
- preg pr;
- /* Processor register. 32 bit */
- preg prp;
- /* Constant/immediate/absolute value. */
- long constant;
- /* CC code. */
- unsigned int cc;
- /* Scaled index mode. */
- unsigned int scale;
- /* Argument type. */
- argtype type;
- /* Size of the argument (in bits) required to represent. */
- int size;
+{
+ /* Register or base register. */
+ reg r;
+ /* Register pair register. */
+ reg rp;
+ /* Index register. */
+ reg i_r;
+ /* Processor register. */
+ preg pr;
+ /* Processor register. 32 bit */
+ preg prp;
+ /* Constant/immediate/absolute value. */
+ long constant;
+ /* CC code. */
+ unsigned int cc;
+ /* Scaled index mode. */
+ unsigned int scale;
+ /* Argument type. */
+ argtype type;
+ /* Size of the argument (in bits) required to represent. */
+ int size;