+#define PPC_OPCODE_VSX 0x8000000ull
+
+/* Opcode is only supported by Power7 architecture. */
+#define PPC_OPCODE_POWER7 0x10000000ull
+
+/* Opcode is supported by A2. */
+#define PPC_OPCODE_A2 0x20000000ull
+
+/* Opcode is supported by PowerPC 476 processor. */
+#define PPC_OPCODE_476 0x40000000ull
+
+/* Opcode is supported by AppliedMicro Titan core */
+#define PPC_OPCODE_TITAN 0x80000000ull
+
+/* Opcode which is supported by the e500 family */
+#define PPC_OPCODE_E500 0x100000000ull
+
+/* Opcode is supported by Power E6500 */
+#define PPC_OPCODE_E6500 0x200000000ull
+
+/* Opcode is supported by Thread management APU */
+#define PPC_OPCODE_TMR 0x400000000ull
+
+/* Opcode which is supported by the VLE extension. */
+#define PPC_OPCODE_VLE 0x800000000ull
+
+/* Opcode is only supported by Power8 architecture. */
+#define PPC_OPCODE_POWER8 0x1000000000ull
+
+/* Opcode is supported by ppc750cl. */
+#define PPC_OPCODE_750 0x2000000000ull
+
+/* Opcode is supported by ppc7450. */
+#define PPC_OPCODE_7450 0x4000000000ull
+
+/* Opcode is supported by ppc821/850/860. */
+#define PPC_OPCODE_860 0x8000000000ull
+
+/* Opcode is only supported by Power9 architecture. */
+#define PPC_OPCODE_POWER9 0x10000000000ull
+
+/* Opcode is supported by e200z4. */
+#define PPC_OPCODE_E200Z4 0x20000000000ull
+
+/* Disassemble to instructions matching later in the opcode table
+ with fewer "mask" bits set rather than the earlist match. Fewer
+ "mask" bits set imply a more general form of the opcode, in fact
+ the underlying machine instruction. */
+#define PPC_OPCODE_RAW 0x40000000000ull
+
+/* Opcode is supported by PowerPC LSP */
+#define PPC_OPCODE_LSP 0x80000000000ull
+
+/* Opcode is only supported by Freescale SPE2 APU. */
+#define PPC_OPCODE_SPE2 0x100000000000ull
+
+/* Opcode is supported by EFS2. */
+#define PPC_OPCODE_EFS2 0x200000000000ull