-#define F_MUL32 0x00000100 /* umul/umulcc/smul/smulcc insns */
-#define F_DIV32 0x00000200 /* udiv/udivcc/sdiv/sdivcc insns */
-#define F_FSMULD 0x00000400 /* 'fsmuld' insn */
-#define F_V8PLUS 0x00000800 /* v9 insns available to 32bit */
-#define F_POPC 0x00001000 /* 'popc' insn */
-#define F_VIS 0x00002000 /* VIS insns */
-#define F_VIS2 0x00004000 /* VIS2 insns */
-#define F_ASI_BLK_INIT 0x00008000 /* block init ASIs */
-#define F_FMAF 0x00010000 /* fused multiply-add */
-#define F_VIS3 0x00020000 /* VIS3 insns */
-#define F_HPC 0x00040000 /* HPC insns */
-#define F_RANDOM 0x00080000 /* 'random' insn */
-#define F_TRANS 0x00100000 /* transaction insns */
-#define F_FJFMAU 0x00200000 /* unfused multiply-add */
-#define F_IMA 0x00400000 /* integer multiply-add */
-#define F_ASI_CACHE_SPARING \
- 0x00800000 /* cache sparing ASIs */
-
-#define F_HWCAP_MASK 0x00ffff00
+#define F_PREFERRED 0x00000080 /* A preferred alias. */
+
+#define F_PREF_ALIAS (F_ALIAS|F_PREFERRED)
+
+/* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_*
+ values precisely. See include/elf/sparc.h. */
+#define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */
+#define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
+#define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */
+#define HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */
+#define HWCAP_POPC 0x00000010 /* 'popc' insn */
+#define HWCAP_VIS 0x00000020 /* VIS insns */
+#define HWCAP_VIS2 0x00000040 /* VIS2 insns */
+#define HWCAP_ASI_BLK_INIT \
+ 0x00000080 /* block init ASIs */
+#define HWCAP_FMAF 0x00000100 /* fused multiply-add */
+#define HWCAP_VIS3 0x00000400 /* VIS3 insns */
+#define HWCAP_HPC 0x00000800 /* HPC insns */
+#define HWCAP_RANDOM 0x00001000 /* 'random' insn */
+#define HWCAP_TRANS 0x00002000 /* transaction insns */
+#define HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */
+#define HWCAP_IMA 0x00008000 /* integer multiply-add */
+#define HWCAP_ASI_CACHE_SPARING \
+ 0x00010000 /* cache sparing ASIs */
+#define HWCAP_AES 0x00020000 /* AES crypto insns */
+#define HWCAP_DES 0x00040000 /* DES crypto insns */
+#define HWCAP_KASUMI 0x00080000 /* KASUMI crypto insns */
+#define HWCAP_CAMELLIA 0x00100000 /* CAMELLIA crypto insns */
+#define HWCAP_MD5 0x00200000 /* MD5 hashing insns */
+#define HWCAP_SHA1 0x00400000 /* SHA1 hashing insns */
+#define HWCAP_SHA256 0x00800000 /* SHA256 hashing insns */
+#define HWCAP_SHA512 0x01000000 /* SHA512 hashing insns */
+#define HWCAP_MPMUL 0x02000000 /* Multiple Precision Multiply */
+#define HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */
+#define HWCAP_PAUSE 0x08000000 /* Pause insn */
+#define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */
+#define HWCAP_CRC32C 0x20000000 /* CRC32C insn */
+
+#define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
+#define HWCAP2_VIS3B 0x00000002 /* Subset of VIS3 present on sparc64 X+. */
+#define HWCAP2_ADP 0x00000004 /* Application Data Protection */
+#define HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */
+#define HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */
+#define HWCAP2_XMPMUL 0x00000020 /* XOR multiple precision multiply */
+#define HWCAP2_XMONT 0x00000040 /* XOR Montgomery mult/sqr instructions */
+#define HWCAP2_NSEC \
+ 0x00000080 /* pause insn with support for nsec timings */
+#define HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */
+#define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */
+#define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */
+
+#define HWCAP2_SPARC6 0x00020000 /* OSA2017 new instructions */
+#define HWCAP2_ONADDSUB 0x00040000 /* Oracle Number add/subtract */
+#define HWCAP2_ONMUL 0x00080000 /* Oracle Number multiply */
+#define HWCAP2_ONDIV 0x00100000 /* Oracle Number divide */
+#define HWCAP2_DICTUNP 0x00200000 /* Dictionary unpack instruction */
+#define HWCAP2_FPCMPSHL 0x00400000 /* Partition compare with shifted result */
+#define HWCAP2_RLE 0x00800000 /* Run-length encoded burst and length */
+#define HWCAP2_SHA3 0x01000000 /* SHA3 instruction */
+