+2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Fix some instruction masks.
+
+2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (REG_82): Removed.
+ (X86_64_82_REG_0): Likewise.
+ (X86_64_82_REG_1): Likewise.
+ (X86_64_82_REG_2): Likewise.
+ (X86_64_82_REG_3): Likewise.
+ (X86_64_82_REG_4): Likewise.
+ (X86_64_82_REG_5): Likewise.
+ (X86_64_82_REG_6): Likewise.
+ (X86_64_82_REG_7): Likewise.
+ (X86_64_82): New.
+ (dis386): Use X86_64_82 instead of REG_82.
+ (reg_table): Remove REG_82.
+ (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
+ X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
+ X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
+ X86_64_82_REG_7.
+
+2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20754
+ * i386-dis.c (REG_82): New.
+ (X86_64_82_REG_0): Likewise.
+ (X86_64_82_REG_1): Likewise.
+ (X86_64_82_REG_2): Likewise.
+ (X86_64_82_REG_3): Likewise.
+ (X86_64_82_REG_4): Likewise.
+ (X86_64_82_REG_5): Likewise.
+ (X86_64_82_REG_6): Likewise.
+ (X86_64_82_REG_7): Likewise.
+ (dis386): Use REG_82.
+ (reg_table): Add REG_82.
+ (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
+ X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
+ X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
+
+2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (REG_82): Renamed to ...
+ (REG_83): This.
+ (dis386): Updated.
+ (reg_table): Likewise.
+
+2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
+ CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_4VNNIW.
+ * i386-opc.h (enum): (AVX512_4VNNIW): New.
+ (i386_cpu_flags): Add cpuavx512_4vnniw.
+ * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
+
+2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
+ PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
+ CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_4FMAPS.
+ (opcode_modifiers): Add ImplicitQuadGroup modifier.
+ * i386-opc.h (AVX512_4FMAP): New.
+ (i386_cpu_flags): Add cpuavx512_4fmaps.
+ (ImplicitQuadGroup): New.
+ (i386_opcode_modifier): Add implicitquadgroup.
+ * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
+
+2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
+ Andrew Waterman <andrew@sifive.com>
+
+ Add support for RISC-V architecture.
+ * configure.ac: Add entry for bfd_riscv_arch.
+ * configure: Regenerate.
+ * disassemble.c (disassembler): Add support for riscv.
+ (disassembler_usage): Likewise.
+ * riscv-dis.c: New file.
+ * riscv-opc.c: New file.
+
+2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
+ (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
+ (rm_table): Update the RM_0FAE_REG_7 entry.
+ * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
+ (cpu_flags): Remove CpuPCOMMIT.
+ * i386-opc.h (CpuPCOMMIT): Removed.
+ (i386_cpu_flags): Remove cpupcommit.
+ * i386-opc.tbl: Remove pcommit.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/20705
+ * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
+ the highest bit in VEX.vvvv for the 3-byte VEX prefix in
+ 32-bit mode. Don't check vex.register_specifier in 32-bit
+ mode.
+ (OP_VEX): Check for invalid mask registers.
+
+2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/20699
+ * i386-dis.c (OP_E_memory): Check addr32flag in stead of
+ sizeflag.
+
+2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/20704
+ * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
+
+2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
+
+ * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
+ local variable to `index_regno'.
+