-
-2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
-
-2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/20799
- * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
- * i386-dis.c (EdqwS): Removed.
- (dqw_swap_mode): Likewise.
- (intel_operand_size): Don't check dqw_swap_mode.
- (OP_E_register): Likewise.
- (OP_E_memory): Likewise.
- (OP_G): Likewise.
- (OP_EX): Likewise.
- * i386-opc.tbl: Remove "S" from EVEX vpextrw.
- * i386-tbl.h: Regerated.
-
-2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Merge AVX512F vmovq.
- * i386-tbl.h: Regerated.
-
-2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/20701
- * i386-dis.c (THREE_BYTE_0F7A): Removed.
- (dis386_twobyte): Don't use THREE_BYTE_0F7A.
- (three_byte_table): Remove THREE_BYTE_0F7A.
-
-2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/20775
- * i386-dis.c (FGRPd9_2): Replace 0 with 1.
- (FGRPd9_4): Replace 1 with 2.
- (FGRPd9_5): Replace 2 with 3.
- (FGRPd9_6): Replace 3 with 4.
- (FGRPd9_7): Replace 4 with 5.
- (FGRPda_5): Replace 5 with 6.
- (FGRPdb_4): Replace 6 with 7.
- (FGRPde_3): Replace 7 with 8.
- (FGRPdf_4): Replace 8 with 9.
- (fgrps): Add an entry for Bad_Opcode.
-
-2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-opc.c (arc_flag_operands): Add F_DI14.
- (arc_flag_classes): Add C_DI14.
- * arc-nps400-tbl.h: Add new exc instructions.
-
-2016-11-03 Graham Markall <graham.markall@embecosm.com>
-
- * arc-dis.c (arc_insn_length): Return length 8 for instructions with
- major opcode 0xa.
- * arc-nps-400-tbl.h: Add dcmac instruction.
- * arc-opc.c (arc_operands): Added operands for dcmac instruction.
- (insert_nps_rbdouble_64): Added.
- (extract_nps_rbdouble_64): Added.
- (insert_nps_proto_size): Added.
- (extract_nps_proto_size): Added.
-
-2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-dis.c (struct arc_operand_iterator): Remove all fields
- relating to long instruction processing, add new limm field.
- (OPCODE): Rename to...
- (OPCODE_32BIT_INSN): ...this.
- (OPCODE_AC): Delete.
- (skip_this_opcode): Handle different instruction lengths, update
- macro name.
- (special_flag_p): Update parameter type.
- (find_format_from_table): Update for more instruction lengths.
- (find_format_long_instructions): Delete.
- (find_format): Update for more instruction lengths.
- (arc_insn_length): Likewise.
- (extract_operand_value): Update for more instruction lengths.
- (operand_iterator_next): Remove code relating to long
- instructions.
- (arc_opcode_to_insn_type): New function.
- (print_insn_arc):Update for more instructions lengths.
- * arc-ext.c (extInstruction_t): Change argument type.
- * arc-ext.h (extInstruction_t): Change argument type.
- * arc-fxi.h: Change type unsigned to unsigned long long
- extensively throughout.
- * arc-nps400-tbl.h: Add long instructions taken from
- arc_long_opcodes table in arc-opc.c.
- * arc-opc.c: Update parameter types on insert/extract handlers.
- (arc_long_opcodes): Delete.
- (arc_num_long_opcodes): Delete.
- (arc_opcode_len): Update for more instruction lengths.
-
-2016-11-03 Graham Markall <graham.markall@embecosm.com>
-
- * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
-
-2016-11-03 Graham Markall <graham.markall@embecosm.com>
-
- * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
- with arc_opcode_len.
- (find_format_long_instructions): Likewise.
- * arc-opc.c (arc_opcode_len): New function.
-
-2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-nps400-tbl.h: Fix some instruction masks.
-
-2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (REG_82): Removed.
- (X86_64_82_REG_0): Likewise.
- (X86_64_82_REG_1): Likewise.
- (X86_64_82_REG_2): Likewise.
- (X86_64_82_REG_3): Likewise.
- (X86_64_82_REG_4): Likewise.
- (X86_64_82_REG_5): Likewise.
- (X86_64_82_REG_6): Likewise.
- (X86_64_82_REG_7): Likewise.
- (X86_64_82): New.
- (dis386): Use X86_64_82 instead of REG_82.
- (reg_table): Remove REG_82.
- (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
- X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
- X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
- X86_64_82_REG_7.
-
-2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/20754
- * i386-dis.c (REG_82): New.
- (X86_64_82_REG_0): Likewise.
- (X86_64_82_REG_1): Likewise.
- (X86_64_82_REG_2): Likewise.
- (X86_64_82_REG_3): Likewise.
- (X86_64_82_REG_4): Likewise.
- (X86_64_82_REG_5): Likewise.
- (X86_64_82_REG_6): Likewise.
- (X86_64_82_REG_7): Likewise.
- (dis386): Use REG_82.
- (reg_table): Add REG_82.
- (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
- X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
- X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
-
-2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (REG_82): Renamed to ...
- (REG_83): This.
- (dis386): Updated.
- (reg_table): Likewise.
-
-2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-
- * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
- * i386-dis-evex.h (evex_table): Updated.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
- CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
- (cpu_flags): Add CpuAVX512_4VNNIW.
- * i386-opc.h (enum): (AVX512_4VNNIW): New.
- (i386_cpu_flags): Add cpuavx512_4vnniw.
- * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Ditto.
-
-2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-
- * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
- PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
- * i386-dis-evex.h (evex_table): Updated.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
- CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
- (cpu_flags): Add CpuAVX512_4FMAPS.
- (opcode_modifiers): Add ImplicitQuadGroup modifier.
- * i386-opc.h (AVX512_4FMAP): New.
- (i386_cpu_flags): Add cpuavx512_4fmaps.
- (ImplicitQuadGroup): New.
- (i386_opcode_modifier): Add implicitquadgroup.
- * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Ditto.
-
-2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
- Andrew Waterman <andrew@sifive.com>
-
- Add support for RISC-V architecture.
- * configure.ac: Add entry for bfd_riscv_arch.
- * configure: Regenerate.
- * disassemble.c (disassembler): Add support for riscv.
- (disassembler_usage): Likewise.
- * riscv-dis.c: New file.
- * riscv-opc.c: New file.
-
-2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
- (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
- (rm_table): Update the RM_0FAE_REG_7 entry.
- * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
- (cpu_flags): Remove CpuPCOMMIT.
- * i386-opc.h (CpuPCOMMIT): Removed.
- (i386_cpu_flags): Remove cpupcommit.
- * i386-opc.tbl: Remove pcommit.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutis/20705
- * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
- the highest bit in VEX.vvvv for the 3-byte VEX prefix in
- 32-bit mode. Don't check vex.register_specifier in 32-bit
- mode.
- (OP_VEX): Check for invalid mask registers.
-
-2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutis/20699
- * i386-dis.c (OP_E_memory): Check addr32flag in stead of
- sizeflag.
-
-2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutis/20704
- * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
-
-2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
-
- * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
- local variable to `index_regno'.
-
-2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
-
- * arc-tbl.h: Removed any "inv.+" instructions from the table.
-
-2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
- usage on ISA basis.
-
-2016-10-11 Jiong Wang <jiong.wang@arm.com>
-
- PR target/20666
- * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
-
-2016-10-07 Jiong Wang <jiong.wang@arm.com>
-
- PR target/20667
- * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
- available.
-
-2016-10-07 Alan Modra <amodra@gmail.com>
-
- * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
-
-2016-10-06 Alan Modra <amodra@gmail.com>
-
- * aarch64-opc.c: Spell fall through comments consistently.
- * i386-dis.c: Likewise.
- * aarch64-dis.c: Add missing fall through comments.
- * aarch64-opc.c: Likewise.
- * arc-dis.c: Likewise.
- * arm-dis.c: Likewise.
- * i386-dis.c: Likewise.
- * m68k-dis.c: Likewise.
- * mep-asm.c: Likewise.
- * ns32k-dis.c: Likewise.
- * sh-dis.c: Likewise.
- * tic4x-dis.c: Likewise.
- * tic6x-dis.c: Likewise.
- * vax-dis.c: Likewise.
-
-2016-10-06 Alan Modra <amodra@gmail.com>
-
- * arc-ext.c (create_map): Add missing break.
- * msp430-decode.opc (encode_as): Likewise.
- * msp430-decode.c: Regenerate.
-
-2016-10-06 Alan Modra <amodra@gmail.com>
-
- * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
- * crx-dis.c (print_insn_crx): Likewise.
-
-2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/20657
- * i386-dis.c (putop): Don't assign alt twice.
-
-2016-09-29 Jiong Wang <jiong.wang@arm.com>
-
- PR target/20553
- * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
-
-2016-09-29 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (L): Make compulsory.
- (LOPT): New, optional form of L.
- (HTM_R): Define as LOPT.
- (L0, L1): Delete.
- (L32OPT): New, optional for 32-bit L.
- (L2OPT): New, 2-bit L for dcbf.
- (SVC_LEC): Update.
- (L2): Define.
- (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
- (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
- <dcbf>: Use L2OPT.
- <tlbiel, tlbie>: Use LOPT.
- <wclr, wclrall>: Use L2.
-
-2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
-
- * Makefile.in: Regenerate.
- * configure: Likewise.
-
-2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-ext-tbl.h (EXTINSN2OPF): Define.
- (EXTINSN2OP): Use EXTINSN2OPF.
- (bspeekm, bspop, modapp): New extension instructions.
- * arc-opc.c (F_DNZ_ND): Define.
- (F_DNZ_D): Likewise.
- (F_SIZEB1): Changed.
- (C_DNZ_D): Define.
- (C_HARD): Changed.
- * arc-tbl.h (dbnz): New instruction.
- (prealloc): Allow it for ARC EM.
- (xbfu): Likewise.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.c (print_immediate_offset_address): Print spaces
- after commas in addresses.
- (aarch64_print_operand): Likewise.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
- rather than "should be" or "expected to be" in error messages.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-dis.c (remove_dot_suffix): New function, split out from...
- (print_mnemonic_name): ...here.
- (print_comment): New function.
- (print_aarch64_insn): Call it.
- * aarch64-opc.c (aarch64_conds): Add SVE names.
- (aarch64_print_operand): Print alternative condition names in
- a comment.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
- (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
- (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
- (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
- (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
- (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
- (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
- (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
- (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
- (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
- (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
- (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
- (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
- (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
- (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
- (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
- (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
- (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
- (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
- (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
- (OP_SVE_XWU, OP_SVE_XXU): New macros.
- (aarch64_feature_sve): New variable.
- (SVE): New macro.
- (_SVE_INSN): Likewise.
- (aarch64_opcode_table): Add SVE instructions.
- * aarch64-opc.h (extract_fields): Declare.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis.c (extract_fields): Make global.
- (do_misc_decoding): Handle the new SVE aarch64_ops.
- * aarch64-dis-2.c: Regenerate.
-
-2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
- (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New