-2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
-
- * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
- (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
- (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
- (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
- (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
- (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
- (WR_s): Update macro.
- (micromips_opcodes): Update register use flags of: "addiu",
- "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
- "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
- "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
- "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
- "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
- "swm" and "xor" instructions.
-
-2011-08-05 David S. Miller <davem@davemloft.net>
-
- * sparc-dis.c (v9a_ast_reg_names): Add "cps".
- (X_RS3): New macro.
- (print_insn_sparc): Handle '4', '5', and '(' format codes.
- Accept %asr numbers below 28.
- * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
- instructions.
-
-2011-08-02 Quentin Neill <quentin.neill@amd.com>
-
- * i386-dis.c (xop_table): Remove spurious bextr insn.
-
-2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
-
- PR ld/13048
- * i386-dis.c (print_insn): Optimize info->mach check.
-
-2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/13046
- * i386-opc.tbl: Add Disp32S to 64bit call.
- * i386-tbl.h: Regenerated.
-
-2011-07-24 Chao-ying Fu <fu@mips.com>
- Maciej W. Rozycki <macro@codesourcery.com>
-
- * micromips-opc.c: New file.
- * mips-dis.c (micromips_to_32_reg_b_map): New array.
- (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
- (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
- (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
- (micromips_to_32_reg_q_map): Likewise.
- (micromips_imm_b_map, micromips_imm_c_map): Likewise.
- (micromips_ase): New variable.
- (is_micromips): New function.
- (set_default_mips_dis_options): Handle microMIPS ASE.
- (print_insn_micromips): New function.
- (is_compressed_mode_p): Likewise.
- (_print_insn_mips): Handle microMIPS instructions.
- * Makefile.am (CFILES): Add micromips-opc.c.
- * configure.in (bfd_mips_arch): Add micromips-opc.lo.
- * Makefile.in: Regenerate.
- * configure: Regenerate.
-
- * mips-dis.c (micromips_to_32_reg_h_map): New variable.
- (micromips_to_32_reg_i_map): Likewise.
- (micromips_to_32_reg_m_map): Likewise.
- (micromips_to_32_reg_n_map): New macro.
-
-2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
-
- * mips-opc.c (NODS): New macro.
- (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
- (DSP_VOLA): Likewise.
- (mips_builtin_opcodes): Add NODS annotation to "deret" and
- "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
- place of TRAP for "wait", "waiti" and "yield".
- * mips16-opc.c (NODS): New macro.
- (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
- (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
- "restore" and "save".
-
-2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * configure.in: Handle bfd_k1om_arch.
- * configure: Regenerated.
-
- * disassemble.c (disassembler): Handle bfd_k1om_arch.
-
- * i386-dis.c (print_insn): Handle bfd_mach_k1om and
- bfd_mach_k1om_intel_syntax.
-
- * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
- ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
- (cpu_flags): Add CpuK1OM.
-
- * i386-opc.h (CpuK1OM): New.
- (i386_cpu_flags): Add cpuk1om.
-
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2011-07-12 Nick Clifton <nickc@redhat.com>
-
- * arm-dis.c (print_insn_arm): Revert previous, undocumented,
- accidental change.
-
-2011-07-01 Nick Clifton <nickc@redhat.com>
-
- PR binutils/12329
- * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
- insns using post-increment addressing.
-
-2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (vex_len_table): Update rorxS.
-
-2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
-
- AVX Programming Reference (June, 2011)
- * i386-dis.c (vex_len_table): Correct rorxS.
-
- * i386-opc.tbl: Correct rorx.
- * i386-tbl.h: Regenerated.
-
-2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
-
- * tilegx-opc.c (find_opcode): Replace "index" with "i".
- * tilepro-opc.c (find_opcode): Likewise.
-
-2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
-
- * mips16-opc.c (jalrc, jrc): Move earlier in file.
-
-2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
- PREFIX_VEX_0F388E.
-
-2011-06-17 Andreas Schwab <schwab@redhat.com>
-
- * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
- (MOSTLYCLEANFILES): ... here.
- * Makefile.in: Regenerate.
-
-2011-06-14 Alan Modra <amodra@gmail.com>
-
- * Makefile.in: Regenerate.
-
-2011-06-13 Walter Lee <walt@tilera.com>
-
- * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
- tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
- * Makefile.in: Regenerate.
- * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
- * configure: Regenerate.
- * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
- * po/POTFILES.in: Regenerate.
- * tilegx-dis.c: New file.
- * tilegx-opc.c: New file.
- * tilepro-dis.c: New file.
- * tilepro-opc.c: New file.
-
-2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
-
- AVX Programming Reference (June, 2011)
- * i386-dis.c (XMGatherQ): New.
- * i386-dis.c (EXxmm_mb): New.
- (EXxmm_mb): Likewise.
- (EXxmm_mw): Likewise.
- (EXxmm_md): Likewise.
- (EXxmm_mq): Likewise.
- (EXxmmdw): Likewise.
- (EXxmmqd): Likewise.
- (VexGatherQ): Likewise.
- (MVexVSIBDWpX): Likewise.
- (MVexVSIBQWpX): Likewise.
- (xmm_mb_mode): Likewise.
- (xmm_mw_mode): Likewise.
- (xmm_md_mode): Likewise.
- (xmm_mq_mode): Likewise.
- (xmmdw_mode): Likewise.
- (xmmqd_mode): Likewise.
- (ymmxmm_mode): Likewise.
- (vex_vsib_d_w_dq_mode): Likewise.
- (vex_vsib_q_w_dq_mode): Likewise.
- (MOD_VEX_0F385A_PREFIX_2): Likewise.
- (MOD_VEX_0F388C_PREFIX_2): Likewise.
- (MOD_VEX_0F388E_PREFIX_2): Likewise.
- (PREFIX_0F3882): Likewise.
- (PREFIX_VEX_0F3816): Likewise.
- (PREFIX_VEX_0F3836): Likewise.
- (PREFIX_VEX_0F3845): Likewise.
- (PREFIX_VEX_0F3846): Likewise.
- (PREFIX_VEX_0F3847): Likewise.
- (PREFIX_VEX_0F3858): Likewise.
- (PREFIX_VEX_0F3859): Likewise.
- (PREFIX_VEX_0F385A): Likewise.
- (PREFIX_VEX_0F3878): Likewise.
- (PREFIX_VEX_0F3879): Likewise.
- (PREFIX_VEX_0F388C): Likewise.
- (PREFIX_VEX_0F388E): Likewise.
- (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
- (PREFIX_VEX_0F38F5): Likewise.
- (PREFIX_VEX_0F38F6): Likewise.
- (PREFIX_VEX_0F3A00): Likewise.
- (PREFIX_VEX_0F3A01): Likewise.
- (PREFIX_VEX_0F3A02): Likewise.
- (PREFIX_VEX_0F3A38): Likewise.
- (PREFIX_VEX_0F3A39): Likewise.
- (PREFIX_VEX_0F3A46): Likewise.
- (PREFIX_VEX_0F3AF0): Likewise.
- (VEX_LEN_0F3816_P_2): Likewise.
- (VEX_LEN_0F3819_P_2): Likewise.
- (VEX_LEN_0F3836_P_2): Likewise.
- (VEX_LEN_0F385A_P_2_M_0): Likewise.
- (VEX_LEN_0F38F5_P_0): Likewise.
- (VEX_LEN_0F38F5_P_1): Likewise.
- (VEX_LEN_0F38F5_P_3): Likewise.
- (VEX_LEN_0F38F6_P_3): Likewise.
- (VEX_LEN_0F38F7_P_1): Likewise.
- (VEX_LEN_0F38F7_P_2): Likewise.
- (VEX_LEN_0F38F7_P_3): Likewise.
- (VEX_LEN_0F3A00_P_2): Likewise.
- (VEX_LEN_0F3A01_P_2): Likewise.
- (VEX_LEN_0F3A38_P_2): Likewise.
- (VEX_LEN_0F3A39_P_2): Likewise.
- (VEX_LEN_0F3A46_P_2): Likewise.
- (VEX_LEN_0F3AF0_P_3): Likewise.
- (VEX_W_0F3816_P_2): Likewise.
- (VEX_W_0F3818_P_2): Likewise.
- (VEX_W_0F3819_P_2): Likewise.
- (VEX_W_0F3836_P_2): Likewise.
- (VEX_W_0F3846_P_2): Likewise.
- (VEX_W_0F3858_P_2): Likewise.
- (VEX_W_0F3859_P_2): Likewise.
- (VEX_W_0F385A_P_2_M_0): Likewise.
- (VEX_W_0F3878_P_2): Likewise.
- (VEX_W_0F3879_P_2): Likewise.
- (VEX_W_0F3A00_P_2): Likewise.
- (VEX_W_0F3A01_P_2): Likewise.
- (VEX_W_0F3A02_P_2): Likewise.
- (VEX_W_0F3A38_P_2): Likewise.
- (VEX_W_0F3A39_P_2): Likewise.
- (VEX_W_0F3A46_P_2): Likewise.
- (MOD_VEX_0F3818_PREFIX_2): Removed.
- (MOD_VEX_0F3819_PREFIX_2): Likewise.
- (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
- (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
- (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
- (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
- (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
- (VEX_LEN_0F3A0E_P_2): Likewise.
- (VEX_LEN_0F3A0F_P_2): Likewise.
- (VEX_LEN_0F3A42_P_2): Likewise.
- (VEX_LEN_0F3A4C_P_2): Likewise.
- (VEX_W_0F3818_P_2_M_0): Likewise.
- (VEX_W_0F3819_P_2_M_0): Likewise.
- (prefix_table): Updated.
- (three_byte_table): Likewise.
- (vex_table): Likewise.
- (vex_len_table): Likewise.
- (vex_w_table): Likewise.
- (mod_table): Likewise.
- (putop): Handle "LW".
- (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
- xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
- vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
- (OP_EX): Likewise.
- (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
- vex_vsib_q_w_dq_mode.
- (OP_XMM): Handle vex_vsib_q_w_dq_mode.
- (OP_VEX): Likewise.
-
- * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
- and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
- CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
- (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
- (opcode_modifiers): Add VecSIB.
-
- * i386-opc.h (CpuAVX2): New.
- (CpuBMI2): Likewise.
- (CpuLZCNT): Likewise.
- (CpuINVPCID): Likewise.
- (VecSIB128): Likewise.
- (VecSIB256): Likewise.
- (VecSIB): Likewise.
- (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
- (i386_opcode_modifier): Add vecsib.
-
- * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
+2012-02-27 Alan Modra <amodra@gmail.com>
+
+ * v850-opc.c (extract_v8): Rearrange to make it obvious this
+ is the inverse of corresponding insert function.
+ (extract_d22, extract_u9, extract_r4): Likewise.
+ (extract_d9): Correct sign extension.
+ (extract_d16_15): Don't assume "long" is 32 bits, and don't
+ rely on implementation defined behaviour for shift right of
+ signed types.
+ (extract_d16_16, extract_d17_16, extract_i9): Likewise.
+ (extract_d23): Likewise, and correct mask.
+
+2012-02-27 Alan Modra <amodra@gmail.com>
+
+ * crx-dis.c (print_arg): Mask constant to 32 bits.
+ * crx-opc.c (cst4_map): Use int array.
+
+2012-02-27 Alan Modra <amodra@gmail.com>
+
+ * arc-dis.c (BITS): Don't use shifts to mask off bits.
+ (FIELDD): Sign extend with xor,sub.
+
+2012-02-25 Walter Lee <walt@tilera.com>
+
+ * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
+ * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
+ TILEPRO_OPC_LW_TLS_SN.
+
+2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.h (HLEPrefixNone): New.
+ (HLEPrefixLock): Likewise.
+ (HLEPrefixAny): Likewise.
+ (HLEPrefixRelease): Likewise.
+
+2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (HLE_Fixup1): New.
+ (HLE_Fixup2): Likewise.
+ (HLE_Fixup3): Likewise.
+ (Ebh1): Likewise.
+ (Evh1): Likewise.
+ (Ebh2): Likewise.
+ (Evh2): Likewise.
+ (Ebh3): Likewise.
+ (Evh3): Likewise.
+ (MOD_C6_REG_7): Likewise.
+ (MOD_C7_REG_7): Likewise.
+ (RM_C6_REG_7): Likewise.
+ (RM_C7_REG_7): Likewise.
+ (XACQUIRE_PREFIX): Likewise.
+ (XRELEASE_PREFIX): Likewise.
+ (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
+ cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
+ Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
+ (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
+ not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
+ MOD_C6_REG_7 and MOD_C7_REG_7.
+ (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
+ (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
+ xtest.
+ (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
+ (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
+
+ * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
+ CPU_RTM_FLAGS.
+ (cpu_flags): Add CpuHLE and CpuRTM.
+ (opcode_modifiers): Add HLEPrefixOk.
+
+ * i386-opc.h (CpuHLE): New.
+ (CpuRTM): Likewise.
+ (HLEPrefixOk): Likewise.
+ (i386_cpu_flags): Add cpuhle and cpurtm.
+ (i386_opcode_modifier): Add hleprefixok.
+
+ * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
+ add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
+ sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
+ operand. Add xacquire, xrelease, xabort, xbegin, xend and
+ xtest.