- * frv-dis.c: Regenerate.
-
-2005-02-07 Jim Blandy <jimb@redhat.com>
-
- * Makefile.am (CGEN): Load guile.scm before calling the main
- application script.
- * Makefile.in: Regenerated.
- * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
- Simply pass the cgen-opc.scm path to ${cgen} as its first
- argument; ${cgen} itself now contains the '-s', or whatever is
- appropriate for the Scheme being used.
-
-2005-01-31 Andrew Cagney <cagney@gnu.org>
-
- * configure: Regenerate to track ../gettext.m4.
-
-2005-01-31 Jan Beulich <jbeulich@novell.com>
-
- * ia64-gen.c (NELEMS): Define.
- (shrink): Generate alias with missing second predicate register when
- opcode has two outputs and these are both predicates.
- * ia64-opc-i.c (FULL17): Define.
- (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
- here to generate output template.
- (TBITCM, TNATCM): Undefine after use.
- * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
- first input. Add ld16 aliases without ar.csd as second output. Add
- st16 aliases without ar.csd as second input. Add cmpxchg aliases
- without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
- ar.ccv as third/fourth inputs. Consolidate through...
- (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
- CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
- * ia64-asmtab.c: Regenerate.
-
-2005-01-27 Andrew Cagney <cagney@gnu.org>
-
- * configure: Regenerate to track ../gettext.m4 change.
-
-2005-01-25 Alexandre Oliva <aoliva@redhat.com>
-
- 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
- * frv-asm.c: Rebuilt.
- * frv-desc.c: Rebuilt.
- * frv-desc.h: Rebuilt.
- * frv-dis.c: Rebuilt.
- * frv-ibld.c: Rebuilt.
- * frv-opc.c: Rebuilt.
- * frv-opc.h: Rebuilt.
-
-2005-01-24 Andrew Cagney <cagney@gnu.org>
-
- * configure: Regenerate, ../gettext.m4 was updated.
-
-2005-01-21 Fred Fish <fnf@specifixinc.com>
-
- * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
- Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
- Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
- * mips-dis.c: Ditto.
-
-2005-01-20 Alan Modra <amodra@bigpond.net.au>
-
- * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
-
-2005-01-19 Fred Fish <fnf@specifixinc.com>
-
- * mips-dis.c (no_aliases): New disassembly option flag.
- (set_default_mips_dis_options): Init no_aliases to zero.
- (parse_mips_dis_option): Handle no-aliases option.
- (print_insn_mips): Ignore table entries that are aliases
- if no_aliases is set.
- (print_insn_mips16): Ditto.
- * mips-opc.c (mips_builtin_opcodes): Add initializer column for
- new pinfo2 member and add INSN_ALIAS initializers as needed. Also
- move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
- * mips16-opc.c (mips16_opcodes): Ditto.
-
-2005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
-
- * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
- (inheritance diagram): Add missing edge.
- (arch_sh1_up): Rename arch_sh_up to match external name to make life
- easier for the testsuite.
- (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
- (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
- (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
- arch_sh2a_or_sh4_up child.
- (sh_table): Do renaming as above.
- Correct comment for ldc.l for gas testsuite to read.
- Remove rogue mul.l from sh1 (duplicate of the one for sh2).
- Correct comments for movy.w and movy.l for gas testsuite to read.
- Correct comments for fmov.d and fmov.s for gas testsuite to read.
-
-2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
-
-2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
-
-2005-01-10 Andreas Schwab <schwab@suse.de>
-
- * disassemble.c (disassemble_init_for_target) <case
- bfd_arch_ia64>: Set skip_zeroes to 16.
- <case bfd_arch_tic4x>: Set skip_zeroes to 32.
-
-2004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
-
- * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
-
-2004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
-
- * avr-dis.c: Prettyprint. Added printing of symbol names in all
- memory references. Convert avr_operand() to C90 formatting.
-
-2004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
-
- * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
-
-2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
-
- * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
- (no_op_insn): Initialize array with instructions that have no
- operands.
- * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
-
-2004-11-29 Richard Earnshaw <rearnsha@arm.com>
-
- * arm-dis.c: Correct top-level comment.
-
-2004-11-27 Richard Earnshaw <rearnsha@arm.com>
-
- * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
- architecuture defining the insn.
- (arm_opcodes, thumb_opcodes): Delete. Move to ...
- * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
- field.
- Also include opcode/arm.h.
- * Makefile.am (arm-dis.lo): Update dependency list.
- * Makefile.in: Regenerate.
-
-2004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
-
- * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
- reflect the change to the short immediate syntax.
-
-2004-11-19 Alan Modra <amodra@bigpond.net.au>
-
- * or32-opc.c (debug): Warning fix.
- * po/POTFILES.in: Regenerate.
-
- * maxq-dis.c: Formatting.
- (print_insn): Warning fix.
-
-2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
-
- * arm-dis.c (WORD_ADDRESS): Define.
- (print_insn): Use it. Correct big-endian end-of-section handling.
-
-2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
- Vineet Sharma <vineets@noida.hcltech.com>
-
- * maxq-dis.c: New file.
- * disassemble.c (ARCH_maxq): Define.
- (disassembler): Add 'print_insn_maxq_little' for handling maxq
- instructions..
- * configure.in: Add case for bfd_maxq_arch.
- * configure: Regenerate.
- * Makefile.am: Add support for maxq-dis.c
- * Makefile.in: Regenerate.
- * aclocal.m4: Regenerate.
-
-2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
-
- * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
- mode.
- * crx-dis.c: Likewise.
-
-2004-11-04 Hans-Peter Nilsson <hp@axis.com>
-
- Generally, handle CRISv32.
- * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
- (struct cris_disasm_data): New type.
- (format_reg, format_hex, cris_constraint, print_flags)
- (get_opcode_entry): Add struct cris_disasm_data * parameter. All
- callers changed.
- (format_sup_reg, print_insn_crisv32_with_register_prefix)
- (print_insn_crisv32_without_register_prefix)
- (print_insn_crisv10_v32_with_register_prefix)
- (print_insn_crisv10_v32_without_register_prefix)
- (cris_parse_disassembler_options): New functions.
- (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
- parameter. All callers changed.
- (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
- failure.
- (cris_constraint) <case 'Y', 'U'>: New cases.
- (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
- for constraint 'n'.
- (print_with_operands) <case 'Y'>: New case.
- (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
- <case 'N', 'Y', 'Q'>: New cases.
- (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
- (print_insn_cris_with_register_prefix)
- (print_insn_cris_without_register_prefix): Call
- cris_parse_disassembler_options.
- * cris-opc.c (cris_spec_regs): Mention that this table isn't used
- for CRISv32 and the size of immediate operands. New v32-only
- entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
- spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
- ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
- Change brp to be v3..v10.
- (cris_support_regs): New vector.
- (cris_opcodes): Update head comment. New format characters '[',
- ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
- Add new opcodes for v32 and adjust existing opcodes to accommodate
- differences to earlier variants.
- (cris_cond15s): New vector.
-
-2004-11-04 Jan Beulich <jbeulich@novell.com>
-
- * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
- (indirEb): Remove.
- (Mp): Use f_mode rather than none at all.
- (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
- replaces what previously was x_mode; x_mode now means 128-bit SSE
- operands.
- (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
- mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
- pinsrw's second operand is Edqw.
- (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
- operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
- fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
- mode when an operand size override is present or always suffixing.
- More instructions will need to be added to this group.
- (putop): Handle new macro chars 'C' (short/long suffix selector),
- 'I' (Intel mode override for following macro char), and 'J' (for
- adding the 'l' prefix to far branches in AT&T mode). When an
- alternative was specified in the template, honor macro character when
- specified for Intel mode.
- (OP_E): Handle new *_mode values. Correct pointer specifications for
- memory operands. Consolidate output of index register.
- (OP_G): Handle new *_mode values.
- (OP_I): Handle const_1_mode.
- (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
- respective opcode prefix bits have been consumed.
- (OP_EM, OP_EX): Provide some default handling for generating pointer
- specifications.
-
-2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
-
- * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
- COP_INST macro.
-
-2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
-
- * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
- (getregliststring): Support HI/LO and user registers.
- * crx-opc.c (crx_instruction): Update data structure according to the
- rearrangement done in CRX opcode header file.
- (crx_regtab): Likewise.
- (crx_optab): Likewise.
- (crx_instruction): Reorder load/stor instructions, remove unsupported
- formats.
- support new Co-Processor instruction 'cpi'.
-
-2004-10-27 Nick Clifton <nickc@redhat.com>
-
- * opcodes/iq2000-asm.c: Regenerate.
- * opcodes/iq2000-desc.c: Regenerate.
- * opcodes/iq2000-desc.h: Regenerate.
- * opcodes/iq2000-dis.c: Regenerate.
- * opcodes/iq2000-ibld.c: Regenerate.
- * opcodes/iq2000-opc.c: Regenerate.
- * opcodes/iq2000-opc.h: Regenerate.
-
-2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
-
- * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
- us4, us5 (respectively).
- Remove unsupported 'popa' instruction.
- Reverse operands order in store co-processor instructions.
-
-2004-10-15 Alan Modra <amodra@bigpond.net.au>
-
- * Makefile.am: Run "make dep-am"
- * Makefile.in: Regenerate.
-
-2004-10-12 Bob Wilson <bob.wilson@acm.org>
-
- * xtensa-dis.c: Use ISO C90 formatting.
-
-2004-10-09 Alan Modra <amodra@bigpond.net.au>
-
- * ppc-opc.c: Revert 2004-09-09 change.
-
-2004-10-07 Bob Wilson <bob.wilson@acm.org>
-
- * xtensa-dis.c (state_names): Delete.
- (fetch_data): Use xtensa_isa_maxlength.
- (print_xtensa_operand): Replace operand parameter with opcode/operand
- pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
- (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
- instruction bundles. Use xmalloc instead of malloc.
-
-2004-10-07 David Gibson <david@gibson.dropbear.id.au>
-
- * ppc-opc.c: Replace literal "0"s with NULLs in pointer
- initializers.
-
-2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
-
- * crx-opc.c (crx_instruction): Support Co-processor insns.
- * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
- (getregliststring): Change function to use the above enum.
- (print_arg): Handle CO-Processor insns.
- (crx_cinvs): Add 'b' option to invalidate the branch-target
- cache.
-
-2004-10-06 Aldy Hernandez <aldyh@redhat.com>
-
- * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
- efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
- efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
- efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
- efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
-
-2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
-
- * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
- rather than add it.
-
-2004-09-30 Paul Brook <paul@codesourcery.com>
-
- * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
- * arm-opc.h: Document %e. Add ARMv6ZK instructions.
-
-2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
-
- * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
- (CONFIG_STATUS_DEPENDENCIES): New.
- (Makefile): Removed.
- (config.status): Likewise.
- * Makefile.in: Regenerated.
-
-2004-09-17 Alan Modra <amodra@bigpond.net.au>
-
- * Makefile.am: Run "make dep-am".
- * Makefile.in: Regenerate.
- * aclocal.m4: Regenerate.
- * configure: Regenerate.
- * po/POTFILES.in: Regenerate.
- * po/opcodes.pot: Regenerate.
-
-2004-09-11 Andreas Schwab <schwab@suse.de>
-
- * configure: Rebuild.
-
-2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
-
- * ppc-opc.c (L): Make this field not optional.
-
-2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
-
- * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
- Fix parameter to 'm[t|f]csr' insns.
-
-2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
-
- * configure.in: Autoupdate to autoconf 2.59.
- * aclocal.m4: Rebuild with aclocal 1.4p6.
- * configure: Rebuild with autoconf 2.59.
- * Makefile.in: Rebuild with automake 1.4p6 (picking up
- bfd changes for autoconf 2.59 on the way).
- * config.in: Rebuild with autoheader 2.59.
-
-2004-08-27 Richard Sandiford <rsandifo@redhat.com>
-
- * frv-desc.[ch], frv-opc.[ch]: Regenerated.
-
-2004-07-30 Michal Ludvig <mludvig@suse.cz>
-
- * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
- (GRPPADLCK2): New define.
- (twobyte_has_modrm): True for 0xA6.
- (grps): GRPPADLCK2 for opcode 0xA6.
-
-2004-07-29 Alexandre Oliva <aoliva@redhat.com>
-
- Introduce SH2a support.
- * sh-opc.h (arch_sh2a_base): Renumber.
- (arch_sh2a_nofpu_base): Remove.
- (arch_sh_base_mask): Adjust.
- (arch_opann_mask): New.
- (arch_sh2a, arch_sh2a_nofpu): Adjust.
- (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
- (sh_table): Adjust whitespace.
- 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
- * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
- instruction list throughout.
- (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
- of arch_sh2a in instruction list throughout.
- (arch_sh2e_up): Accomodate above changes.
- (arch_sh2_up): Ditto.
- 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
- * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
- 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
- * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
- * sh-opc.h (arch_sh2a_nofpu): New.
- (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
- (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
- instruction.
- 2004-01-20 DJ Delorie <dj@redhat.com>
- * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
- 2003-12-29 DJ Delorie <dj@redhat.com>
- * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
- sh_opcode_info, sh_table): Add sh2a support.
- (arch_op32): New, to tag 32-bit opcodes.
- * sh-dis.c (print_insn_sh): Support sh2a opcodes.
- 2003-12-02 Michael Snyder <msnyder@redhat.com>
- * sh-opc.h (arch_sh2a): Add.
- * sh-dis.c (arch_sh2a): Handle.
- * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
-
-2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
-
- * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.