-
-2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
-
- * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
- (SYMTAB_AVAILABLE): Removed.
- (#include "elf/aarch64.h): Ditto.
-
-2013-06-17 Catherine Moore <clm@codesourcery.com>
- Maciej W. Rozycki <macro@codesourcery.com>
- Chao-Ying Fu <fu@mips.com>
-
- * micromips-opc.c (EVA): Define.
- (TLBINV): Define.
- (micromips_opcodes): Add EVA opcodes.
- * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
- (print_insn_args): Handle EVA offsets.
- (print_insn_micromips): Likewise.
- * mips-opc.c (EVA): Define.
- (TLBINV): Define.
- (mips_builtin_opcodes): Add EVA opcodes.
-
-2013-06-17 Alan Modra <amodra@gmail.com>
-
- * Makefile.am (mips-opc.lo): Add rules to create automatic
- dependency files. Pass archdefs.
- (micromips-opc.lo, mips16-opc.lo): Likewise.
- * Makefile.in: Regenerate.
-
-2013-06-14 DJ Delorie <dj@redhat.com>
-
- * rx-decode.opc (rx_decode_opcode): Bit operations on
- registers are 32-bit operations, not 8-bit operations.
- * rx-decode.c: Regenerate.
-
-2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
-
- * micromips-opc.c (IVIRT): New define.
- (IVIRT64): New define.
- (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
- tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
-
- * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
- dmtgc0 to print cp0 names.
-
-2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
-
- * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
- argument.
-
-2013-06-08 Catherine Moore <clm@codesourcery.com>
- Richard Sandiford <rdsandiford@googlemail.com>
-
- * micromips-opc.c (D32, D33, MC): Update definitions.
- (micromips_opcodes): Initialize ase field.
- * mips-dis.c (mips_arch_choice): Add ase field.
- (mips_arch_choices): Initialize ase field.
- (set_default_mips_dis_options): Declare and setup mips_ase.
- * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
- MT32, MC): Update definitions.
- (mips_builtin_opcodes): Initialize ase field.
-
-2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
-
- * s390-opc.txt (flogr): Require a register pair destination.
-
-2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
- instruction format.
-
-2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
-
- * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
-
-2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
- * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
- XLS_MASK, PPCVSX2): New defines.
- (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
- fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
- mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
- mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
- mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
- vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
- vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
- vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
- vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
- vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
- vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
- vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
- vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
- vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
- xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
- xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
- xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
- xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
- <lxvx, stxvx>: New extended mnemonics.
-
-2013-05-17 Alan Modra <amodra@gmail.com>
-
- * ia64-raw.tbl: Replace non-ASCII char.
- * ia64-waw.tbl: Likewise.
- * ia64-asmtab.c: Regenerate.
-
-2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
-
- * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.