+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * arm-dis.c (arm_opcodes): Add SEVL.
+ (thumb_opcodes): Likewise.
+ (thumb32_opcodes): Likewise.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * arm-dis.c (data_barrier_option): New function.
+ (print_insn_arm): Use data_barrier_option.
+ (print_insn_thumb32): Use data_barrier_option.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
+
+ * arm-dis.c (COND_UNCOND): New constant.
+ (print_insn_coprocessor): Add support for %u format specifier.
+ (print_insn_neon): Likewise.
+
+2012-08-21 David S. Miller <davem@davemloft.net>
+
+ * sparc-opc.c (4-argument crypto instructions): Fix encoding using
+ F3F4 macro.
+
+2012-08-20 Edmar Wienskoski <edmar@freescale.com>
+
+ * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
+ vabsduh, vabsduw, mviwsplt.
+
+2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
+
+ * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
+ CPU_BTVER2_FLAGS.
+
+ * i386-opc.h: Update CpuPRFCHW comment.
+
+ * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2012-08-17 Nick Clifton <nickc@redhat.com>
+
+ * po/uk.po: New Ukranian translation.
+ * configure.in (ALL_LINGUAS): Add uk.
+ * configure: Regenerate.
+
+2012-08-16 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
+ RBX for the third operand.
+ <"lswi">: Use RAX for second and NBI for the third operand.
+
+2012-08-15 DJ Delorie <dj@redhat.com>
+
+ * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
+ operands, so that data addresses can be corrected when not
+ ES-overridden.
+ * rl78-decode.c: Regenerate.
+ * rl78-dis.c (print_insn_rl78): Make order of modifiers
+ irrelevent. When the 'e' specifier is used on an operand and no
+ ES prefix is provided, adjust address to make it absolute.
+
+2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
+
+2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
+
+2012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
+ macros, use local variables for info struct member accesses,
+ update the type of the variable used to hold the instruction
+ word.
+ (print_insn_mips, print_mips16_insn_arg): Likewise.
+ (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
+ local variables for info struct member accesses.
+ (print_insn_micromips): Add GET_OP_S local macro.
+ (_print_insn_mips): Update the type of the variable used to hold
+ the instruction word.
+
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * Makefile.am: Add AArch64.
+ * Makefile.in: Regenerate.
+ * aarch64-asm.c: New file.
+ * aarch64-asm.h: New file.
+ * aarch64-dis.c: New file.
+ * aarch64-dis.h: New file.
+ * aarch64-gen.c: New file.
+ * aarch64-opc.c: New file.
+ * aarch64-opc.h: New file.
+ * aarch64-tbl.h: New file.
+ * configure.in: Add AArch64.
+ * configure: Regenerate.
+ * disassemble.c: Add AArch64.
+ * aarch64-asm-2.c: New file (automatically generated).
+ * aarch64-dis-2.c: New file (automatically generated).
+ * aarch64-opc-2.c: New file (automatically generated).
+ * po/POTFILES.in: Regenerate.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c (micromips_opcodes): Update comment.
+ * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
+ instructions for IOCT as appropriate.
+ * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
+ opcode_is_member.
+ * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
+ the result of a check for the -Wno-missing-field-initializers
+ GCC option.
+ * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
+ (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
+ compilation.
+ (mips16-opc.lo): Likewise.
+ (micromips-opc.lo): Likewise.
+ * aclocal.m4: Regenerate.
+ * configure: Regenerate.
+ * Makefile.in: Regenerate.
+
+2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
+
+ PR gas/14423
+ * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
+ * i386-init.h: Regenerated.
+
+2012-08-09 Nick Clifton <nickc@redhat.com>
+
+ * po/vi.po: Updated Vietnamese translation.
+
+2012-08-07 Roland McGrath <mcgrathr@google.com>
+
+ * i386-dis.c (reg_table): Fill out REG_0F0D table with
+ AMD-reserved cases as "prefetch".
+ (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
+ (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
+ (reg_table): Use those under REG_0F18.
+ (mod_table): Add those cases as "nop/reserved".
+
+2012-08-07 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
+
+2012-08-06 Roland McGrath <mcgrathr@google.com>
+
+ * i386-dis.c (print_insn): Print spaces between multiple excess
+ prefixes. Return actual number of excess prefixes consumed,
+ not always one.
+
+ * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
+
+2012-08-06 Roland McGrath <mcgrathr@google.com>
+ Victor Khimenko <khim@google.com>
+ H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
+ (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
+ (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
+ (OP_E_register): Likewise.
+ (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
+