+start-sanitize-v850e
+Fri Sep 19 11:45:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2.
+
+end-sanitize-v850e
+Thu Sep 18 11:21:43 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr.
+
+Tue Sep 16 15:18:20 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (v850_opcodes): Further rearrangements.
+
+start-sanitize-d30v
+Tue Sep 16 16:12:11 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ * d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change.
+
+end-sanitize-d30v
+Tue Sep 16 09:48:50 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (v850_opcodes): Fields reordered to allow assembler
+ parser to work.
+
+Tue Sep 16 10:01:00 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret.
+start-sanitize-tx19
+ * mips16-opc.c: Added mips16 sdbbp.
+end-sanitize-tx19
+
+Mon Sep 15 18:31:52 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c: Initialise processors field of v850_opcode structure.
+
+start-sanitize-d30v
+Wed Aug 27 21:42:39 1997 Ken Raeburn <raeburn@cygnus.com>
+
+ Merge changes from Martin Hunt:
+
+ * d30v-opc.c: Change mvfacc to accept 6-bit unsigned values.
+
+ * d30v-opc.c (pre_defined_registers): Add control registers from 0-63.
+ (d30v_opcode_tabel): Add dbt, rtd, srah, and srlh instructions. Fix
+ rot2h, sra2h, and srl2h to use new SHORT_A5S format.
+
+ * d30v-dis.c (print_insn): Fix disassembly of SHORT_D2 opcodes.
+
+ * d30v-dis.c (print_insn): First operand of d*i (delayed
+ branch) instructions is relative.
+
+ * d30v-opc.c (d30v_opcode_table): Change form for repeati.
+ (d30v_operand_table): Add IMM6S3 type.
+ (d30v_format_table): Change SHORT_D2. Add LONG_Db.
+
+ * d30v-dis.c: Fix bug with ".s" and ".l" extensions
+ and cmp instructions.
+
+ * d30v-opc.c: Correct entries for repeat*, and sat*.
+ Make IMM5 unsigned. Create IMM6U and IMM12S3U operand
+ types. Correct several formats.
+
+ * d30v-opc.c: (pre_defined_registers): Add dpsw and dpc.
+
+ * d30v-opc.c (pre_defined_registers): Change control registers.
+
+ * d30v-opc.c (d30v_format_table): Correct SHORT_C1 and
+ SHORT_C2. Manual was incorrect.
+
+ * d30v-dis.c (lookup_opcode): Return value now indicates
+ if an opcode has a short and a long form. Used for deciding
+ to append a ".s" or ".l".
+ (print_insn): Append a ".s" to an instruction if it is
+ the short form and ".l" if it is a long form. Do not append
+ anything if the instruction has only one possible size.
+
+ * d30v-opc.c: Change mulx2h to require an even register.
+ New form: SHORT_A2; a SHORT_A form that needs an even
+ register as the first operand.
+
+ * d30v-dis.c (print_insn_d30v): Fix problem where the last
+ instruction was not being disassembled if there were an odd
+ number of instructions.
+
+ * d30v-opc.c (SHORT_M2, LONG_M2): Two new forms.
+
+end-sanitize-d30v
+start-sanitize-v850e
+Fri Sep 12 11:43:54 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (disassemble): Improved display of register lists.
+
+end-sanitize-v850e
+Thu Sep 11 17:35:10 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc-opc.c (sparc_opcodes): Fix assembler args to
+ fzeros, fones, fsrc1, fsrc1s, fsrc2s, fnot1, fnot1s, fnot2s,
+ fors, fnors, fands, fnands, fxors, fxnors, fornot1s, fornot2s,
+ fandnot1s, fandnot2s.
+
+Tue Sep 9 10:03:49 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq.
+
+Mon Sep 8 14:06:59 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * cgen-asm.c (cgen_parse_address): New argument resultp.
+ All callers updated.
+ * m32r-asm.c (parse_h_hi16): Right shift numbers by 16.
+
+Tue Sep 2 18:39:08 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-dis.c (disassemble): PC relative instructions are
+ relative to the next instruction, not the current instruction.
+
+Tue Sep 2 15:41:55 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (disassemble): Only signed extend values that are not
+ returned by extract functions.
+ Remove use of V850_OPERAND_ADJUST_SHORT_MEMORY flag.
+
+Tue Sep 2 15:39:40 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c: Update comments. Remove use of
+ V850_OPERAND_ADJUST_SHORT_MEMORY. Fix several operand patterns.
+
+Tue Aug 26 09:42:28 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (MOVHI): Immediate parameter is unsigned.
+
+Mon Aug 25 15:58:07 1997 Christopher Provenzano <proven@cygnus.com>
+
+ * configure: Rebuilt with latest devo autoconf for NT support.
+
+Fri Aug 22 10:35:15 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-dis.c (disassemble): Use curly brace syntax for register
+ lists.
+
+ * v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases
+ where r0 is being used as a destination register.
+
+start-sanitize-v850e
+Thu Aug 21 11:09:09 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other.
+end-sanitize-v850e
+
+start-sanitize-sh4
+Wed Aug 20 00:43:11 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh-opc.h (sh_arg_type): Add A_SGR and A_DBR.
+ (sh_nibble_type, sh_arg_type): Add SH4 floating point extensions.
+ (sh_table): Likewise. Add movca.l, ocbi, ocbp, ocbwb.
+ Add insns to access SGR and DBR.
+ * sh-dis.c (print_insn_shx): Add SH4 floating point extensions.
+
+end-sanitize-sh4
+Tue Aug 19 10:59:59 1997 Richard Henderson <rth@cygnus.com>
+
+ * alpha-opc.c (alpha_opcodes): Fix hw_rei_stall mungage.
+
+Mon Aug 18 11:10:03 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850-opc.c (v850_opcodes[]): Remove use of flag field.
+start-sanitize-v850eq
+ * v850-opc.c (v850_opcodes[]): Add support for reversed short load
+ opcodes..
+end-sanitize-v850eq
+
+start-sanitize-v850e
+Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com>
+
+ * configure (cgen_files): Add support for v850e target.
+ * configure.in (cgen_files): Add support for v850e target.
+end-sanitize-v850e
+
+start-sanitize-v850eq
+Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com>
+
+ * configure (cgen_files): Add support for v850eq target.
+ * configure.in (cgen_files): Add support for v850eq target.
+end-sanitize-v850eq
+
+Fri Aug 15 05:17:48 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * configure.in (bfd_arc_arch): Add.
+ * configure: Rebuild.
+ * Makefile.am (ALL_MACHINES): Add arc-dis.lo, arc-opc.lo.
+ * Makefile.in: Rebuild.
+ * arc-dis.c, arc-opc.c: New files.
+ * disassemble.c (ARCH_all): Define ARCH_arc.
+ (disassembler): Add ARC support.
+
+Wed Aug 13 18:52:11 1997 Nick Clifton <nickc@cygnus.com>
+
+start-sanitize-v850eq
+ * v850-dis.c (disassemble): Add support for v850EQ instructions.
+
+ * v850-opc.c (insert_i5div, extract_i5div): New Functions.
+ (v850_opcodes): Add v850EQ instructions.
+end-sanitize-v850eq
+start-sanitize-v850e
+ * v850-dis.c (disassemble): Add support for v850E instructions.
+
+ * v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16,
+ extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9,
+ insert_spe, extract_spe): New Functions.
+ (v850_opcodes): Add v850E instructions.
+end-sanitize-v850e
+
+ * v850-opc.c: Reorganised and re-layed out to improve readability
+ and portability.
+
+Tue Aug 5 23:09:31 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure: Rebuild with autoconf 2.12.1.
+
+Mon Aug 4 12:02:16 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * aclocal.m4, configure: Rebuild with new automake patches.
+
+Fri Aug 1 13:02:04 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure.in: Set enable_shared before AM_PROG_LIBTOOL.
+ * acinclude.m4: Just include acinclude.m4 from BFD.
+ * aclocal.m4, configure: Rebuild.
+
+Thu Jul 31 21:44:42 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.am: New file, based on old Makefile.in.
+ * acconfig.h: New file.
+ * acinclude.m4: New file.
+ * stamp-h.in: New file.
+ * configure.in: Call AM_INIT_AUTOMAKE and AM_PROG_LIBTOOL.
+ Removed shared library handling; now handled by libtool. Replace
+ AC_CONFIG_HEADER with AM_CONFIG_HEADER. Call AM_MAINTAINER_MODE,
+ AM_CYGWIN32, and AM_EXEEXT. Replace AC_PROG_INSTALL with
+ AM_PROG_INSTALL. Change all .o files to .lo. Remove stamp-h
+ handling in AC_OUTPUT.
+ * dep-in.sed: Change .o to .lo.
+ * Makefile.in: Now built with automake.
+ * aclocal.m4: Now built with aclocal.
+ * config.in, configure: Rebuild.
+
+Mon Jul 28 21:52:24 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c: Fix typo/thinko in "eret" instruction.
+
+start-sanitize-r5900
+Mon Jul 28 22:07:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips-opc.c: Fix coding of mtsa.
+
+end-sanitize-r5900
+Thu Jul 24 13:03:26 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns.
+ Make array const.
+ * sparc-dis.c (sorted_opcodes): New static local.
+ (struct opcode_hash): `opcode' is pointer to const element.
+ (build_hash): First arg is now table of sorted pointers.
+ (print_insn_sparc): Sort opcodes by sorting table of pointers.
+ (compare_opcodes): Update.
+
+Tue Jul 15 12:05:23 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * cgen-opc.c: #include <ctype.h>.
+ (hash_keyword_name): New arg `case_sensitive_p'. Callers updated.
+ Handle case insensitive hashing.
+ (hash_keyword_value): Change type of `value' to unsigned int.
+
+Thu Jul 10 12:56:10 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (mips_builtin_opcodes): If an insn uses single
+ precision FP, mark it as such. Likewise for double precision
+ FP. Mark ISA1 insns. Consolidate duplicate opcodes where
+ possible.
+start-sanitize-r5900
+ (mips_builtin_opcodes): Remove non-existant r5900 instructions
+end-sanitize-r5900
+
+start-sanitize-r5900
+Thu Jun 26 16:20:27 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (mips_builtin_opcodes): Add "pinteh", "pexeh" and
+ "pexew" as synonyms for "pintoh", "pexoh", "pexow".
+
+end-sanitize-r5900
+Wed Jun 25 15:25:57 1997 Felix Lee <flee@cirdan.cygnus.com>
+
+ * ppc-opc.c (extract_nsi): make unsigned expression signed before
+ negating it.
+ (UNUSED): remove one level of parens, so MSVC doesn't choke on
+ nesting depth when all the macros are expanded.
+
+Tue Jun 17 17:02:17 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * sparc-opc.c: The fcmp v9a instructions take an integer register
+ as a destination, not a floating point register. From Christian
+ Kuehnke <Christian.Kuehnke@arbi.Informatik.Uni-Oldenburg.DE>.
+
+Mon Jun 16 14:13:18 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@()
+ syntax. From Roman Hodek
+ <rnhodek@faui22c.informatik.uni-erlangen.de>.
+
+ * i386-dis.c (twobyte_has_modrm): Fix pand.
+
+Mon Jun 16 14:08:38 1997 Michael Taylor <mbt@mit.edu>
+
+ * i386-dis.c (dis386_twobyte): Fix pand and pandn.
+
+Tue Jun 10 11:26:47 1997 H.J. Lu <hjl@gnu.ai.mit.edu>
+
+ * arm-dis.c: Add prototypes for arm_decode_shift and
+ print_insn_arm.
+
+Mon Jun 2 11:39:04 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: Add r3900 insns.
+
+Tue May 27 15:55:44 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * sh-dis.c (print_insn_shx): Change relmask to bfd_vma. Don't
+ print delay slot instructions on the same line. When using a PC
+ relative load, add a comment with the value being loaded if it can
+ be obtained.
+