+Tue Oct 29 12:22:21 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-opc.c (D9_RELAX): Renamed from D9, all references
+ changed.
+ (v850_operands): Make sure D22 immediately follows D9_RELAX.
+
+end-sanitize-v850
+Fri Oct 25 12:12:53 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5.
+
+start-sanitize-v850
+Thu Oct 24 17:53:52 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-opc.c (insert_d8_6): Fix operand insertion for sld.w
+ and sst.w instructions.
+
+ * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for
+ "bCC"instructions).
+
+end-sanitize-v850
+Thu Oct 24 17:21:20 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (_print_insn_mips): Use a tab between the instruction
+ and the arguments.
+
+Tue Oct 22 23:32:56 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * ppc-opc.c (PPCPWR2): Define.
+ (powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating
+ it.
+
+Fri Oct 11 16:03:49 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode
+ field for movhu instruction.
+start-sanitize-v850
+
+ * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
+ cast value to "long" not "signed long" to keep hpux10
+ compiler quiet.
+end-sanitize-v850
+
+Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field
+ for mov (abs16),DN.
+
+ * mn10300-opc.c (FMT*): Remove definitions.
+
+ * mn10300-opc.c (mn10300_opcodes): Fix destination register
+ for shift-by-register opcodes.
+
+ * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM
+ into [AD][MN][01] for encoding the position of the register
+ in the opcode.
+
+Wed Oct 9 11:19:26 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
+ "putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
+
+Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c (mn10300_operands): Remove "REGS" operand.
+ Fix various typos. Add "PAREN" operand.
+ (MEM, MEM2): Define.
+ (mn10300_opcodes): Surround all memory addresses with "PAREN"
+ operands. Fix several typos.
+
+ * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's
+ changes.
+
+Mon Oct 7 16:48:45 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c (FMT_XX): Renumber starting at one.
+ (mn10300_operands): Rough cut. Enough to parse "mov" instructions
+ at this time.
+ (mn10300_opcodes): Break opcode format out into its own field.
+ Update many operand fields to deal with signed vs unsigned
+ issues. Fix one or two typos in the "mov" instruction
+ opcode, mask and/or operand fields.
+
+Mon Oct 7 11:39:49 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-opc.c (plusha): Prefer encoding for m68040up, in case
+ m68851 wasn't reset.
+
+Thu Oct 3 17:17:02 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for
+ all opcodes. Very rough cut at operands for all opcodes.
+
+ * mn10300-opc.c (mn10300_opcodes): Start fleshing out the
+ opcode table.
+
+Thu Oct 3 10:06:07 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c, mn10300-opc.c: New files.
+ * mn10200-dis.c, mn10300-dis.c: New files.
+ * mn10x00-opc.c, mn10x00-dis.c: Deleted.
+ * disassemble.c: Break mn10x00 support into 10200 and 10300
+ support.
+ * configure.in: Likewise.
+ * configure: Rebuilt.
+
+Thu Oct 3 15:59:12 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
+
+ * Makefile.in (MOSTLYCLEAN): Move config.log to distclean.
+
+Wed Oct 2 23:28:42 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita
+ MN10x00 processors.
+ * disassemble (ARCH_mn10x00): Define.
+ (disassembler): Handle bfd_arch_mn10x00.
+ * configure.in: Recognize bfd_mn10x00_arch.
+ * configure: Rebuilt.
+
+Tue Oct 1 10:49:11 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses
+ accordingly. Don't declare functions using op_rtn.
+
+start-sanitize-v850
+Fri Sep 27 18:28:59 1996 Stu Grossman (grossman@critters.cygnus.com)
+
+ * v850-dis.c (disassemble): Add memaddr argument. Re-arrange
+ params to be more standard.
+ * (disassemble): Print absolute addresses and symbolic names for
+ branch and jump targets.
+ * v850-opc.c (v850_operand): Add displacement flag to 9 and 22
+ bit operands.
+ * (v850_opcodes): Add breakpoint insn.
+
+end-sanitize-v850
+Mon Sep 23 12:32:26 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-opc.c: Move the fmovemx data register cases before the
+ other cases, so that they get recognized before the data register
+ does gets treated as a degenerate register list.
+
+Tue Sep 17 12:06:51 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-opc.c: Add a case for "div" and "divu" with two registers
+ and a destination of $0.
+
+Tue Sep 10 16:12:39 1996 Fred Fish <fnf@rtl.cygnus.com>
+
+ * mips-dis.c (print_insn_arg): Add prototype.
+ (_print_insn_mips): Ditto.
+
+Mon Sep 9 14:26:26 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (print_insn_arg): Print condition code registers as
+ $fccN.
+
+Tue Sep 3 12:09:46 1996 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx.
+
+start-sanitize-v850
+Tue Sep 3 12:05:25 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-dis.c (disassemble): Make static. Provide prototype.
+
+Sun Sep 1 22:30:40 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-opc.c (insert_d9, insert_d22): Fix boundary case
+ in range checks.
+
+Sat Aug 31 01:27:26 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-dis.c (disassemble): Handle insertion of ',', '[' and
+ ']' characters into the output stream.
+ * v850-opc.c (v850_opcodes: Remove size field from all opcodes.
+ Add "memop" field to all opcodes (for the disassembler).
+ Reorder opcodes so that "nop" comes before "mov" and "jr"
+ comes before "jarl".
+
+ * v850-dis.c (print_insn_v850): Fix typo in last change.
+
+ * v850-dis.c (print_insn_v850): Properly handle disassembling
+ a two byte insn at the end of a memory region when the memory
+ region's size is only two byte aligned.
+
+ * v850-dis.c (v850_cc_names): Fix stupid thinkos.
+
+ * v850-dis.c (v850_reg_names): Define.
+ (v850_sreg_names, v850_cc_names): Likewise.
+ (disassemble): Very rough cut at printing operands (unformatted).
+
+ * v850-opc.c (BOP_MASK): Fix.
+ (v850_opcodes): Fix mask for jarl and jr.
+
+ * v850-dis.c: New file. Skeleton for disassembler support.
+ * Makefile.in Remove v850 references, they're not needed here
+ and they weren't being sanitized away.
+ * configure.in: Add v850-dis.o when building v850 toolchains.
+ * configure: Rebuilt.
+ * disassemble.c (disassembler): Call v850 disassembler.
+
+ * v850-opc.c (insert_d8_7, extract_d8_7): New functions.
+ (insert_d8_6, extract_d8_6): New functions.
+ (v850_operands): Rename D7S to D7; operand for D7 is unsigned.
+ Rename D8 to D8_7, use {insert,extract}_d8_7 routines.
+ Add D8_6.
+ (IF4A, IF4B): Use "D7" instead of "D7S".
+ (IF4C, IF4D): Use "D8_7" instead of "D8".
+ (IF4E, IF4F): New. Use "D8_6".
+ (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for
+ sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w.
+
+ * v850-opc.c (insert_d16_15, extract_d16_15): New functions.
+ (v850_operands): Change D16 to D16_15, use special insert/extract
+ routines. New new D16 that uses the generic insert/extract code.
+ (IF7A, IF7B): Use D16_15.
+ (IF7C, IF7D): New. Use D16.
+ (v850_opcodes): Use IF7C and IF7D for ld.b and st.b.
+
+ * v850-opc.c (insert_d9, insert_d22): Slightly improve error
+ message. Issue an error if the branch offset is odd.
+
+ * v850-opc.c: Add notes about needing special insert/extract
+ for all the load/store insns, except "ld.b" and "st.b".
+
+ * v850-opc.c (insert_d22, extract_d22): New functions.
+ (v850_operands): Use insert_d22 and extract_d22 for
+ D22 operands.
+ (insert_d9): Fix range check.
+
+Fri Aug 30 18:01:02 1996 J.T. Conklin <jtc@hippo.cygnus.com>
+
+ * v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flag
+ and set bits field to D9 and D22 operands.
+
+Thu Aug 29 11:10:46 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-opc.c (v850_operands): Define SR2 operand.
+ (v850_opcodes): "ldsr" uses R1,SR2.
+
+ * v850-opc.c (v850_opcodes): Fix opcode specs for
+ sld.w, sst.b, sst.h, sst.w, and nop.
+
+Wed Aug 28 15:55:43 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-opc.c (v850_opcodes): Add null opcode to mark the
+ end of the opcode table.
+
+end-sanitize-v850
+start-sanitize-d10v
+Mon Aug 26 13:35:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-opc.c (pre_defined_registers): Added register pairs,
+ "r0-r1", "r2-r3", etc.
+
+end-sanitize-d10v
+start-sanitize-v850