x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMD

[deliverable/binutils-gdb.git] / opcodes / aarch64-asm.c

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index da1750b94e9db54fe6a4ec0c6261c11b595e37bb..36f84e800ed5e12bfc62ee005e4ffe317a49dac4 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1,5 +1,5 @@
 /* aarch64-asm.c -- AArch64 assembler support.
 /* aarch64-asm.c -- AArch64 assembler support.

-   Copyright (C) 2012-2019 Free Software Foundation, Inc.
+   Copyright (C) 2012-2020 Free Software Foundation, Inc.

    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.


@@ -130,6 +130,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
       switch (info->qualifier)
        {
        case AARCH64_OPND_QLF_S_4B:
       switch (info->qualifier)
        {
        case AARCH64_OPND_QLF_S_4B:

+       case AARCH64_OPND_QLF_S_2H:

          /* L:H */
          assert (reglane_index < 4);
          insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
          /* L:H */
          assert (reglane_index < 4);
          insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);


@@ -618,17 +619,6 @@ aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
   return TRUE;
 }
 
   return TRUE;
 }
 

-/* Encode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!.  */
-bfd_boolean
-aarch64_ins_addr_simple_2 (const aarch64_operand *self,
-                          const aarch64_opnd_info *info, aarch64_insn *code,
-                          const aarch64_inst *inst,
-                          aarch64_operand_error *errors)
-
-{
-  return aarch64_ins_addr_simple (self, info, code, inst, errors);
-}
-

 /* Encode the address operand for e.g.
      STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
 bfd_boolean
 /* Encode the address operand for e.g.
      STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
 bfd_boolean


@@ -1252,8 +1242,9 @@ aarch64_ins_sve_shrimm (const aarch64_operand *self,
   const aarch64_opnd_info *prev_operand;
   unsigned int esize;
 
   const aarch64_opnd_info *prev_operand;
   unsigned int esize;
 

-  assert (info->idx > 0);
-  prev_operand = &inst->operands[info->idx - 1];
+  unsigned int opnd_backshift = get_operand_specific_data (self);
+  assert (info->idx >= (int)opnd_backshift);
+  prev_operand = &inst->operands[info->idx - opnd_backshift];

   esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
   insert_all_fields (self, code, 16 * esize - info->imm.value);
   return TRUE;
   esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
   insert_all_fields (self, code, 16 * esize - info->imm.value);
   return TRUE;


@@ -1624,6 +1615,7 @@ do_special_encoding (struct aarch64_inst *inst)
 static void
 aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
 {
 static void
 aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
 {

+  int variant = 0;

   switch (inst->opcode->iclass)
     {
     case sve_cpy:
   switch (inst->opcode->iclass)
     {
     case sve_cpy:


@@ -1634,6 +1626,8 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
     case sve_index:
     case sve_shift_pred:
     case sve_shift_unpred:
     case sve_index:
     case sve_shift_pred:
     case sve_shift_unpred:

+    case sve_shift_tsz_hsd:
+    case sve_shift_tsz_bhsd:

       /* For indices and shift amounts, the variant is encoded as
         part of the immediate.  */
       break;
       /* For indices and shift amounts, the variant is encoded as
         part of the immediate.  */
       break;


@@ -1666,10 +1660,33 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
       insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) + 1, 0);
       break;
 
       insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) + 1, 0);
       break;
 

+    case sve_size_bh:

     case sve_size_sd:
       insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
       break;
 
     case sve_size_sd:
       insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
       break;
 

+    case sve_size_sd2:
+      insert_field (FLD_SVE_sz2, &inst->value, aarch64_get_variant (inst), 0);
+      break;
+
+    case sve_size_hsd2:
+      insert_field (FLD_SVE_size, &inst->value,
+                   aarch64_get_variant (inst) + 1, 0);
+      break;
+
+    case sve_size_tsz_bhs:
+      insert_fields (&inst->value,
+                    (1 << aarch64_get_variant (inst)),
+                    0, 2, FLD_SVE_tszl_19, FLD_SVE_sz);
+      break;
+
+    case sve_size_13:
+      variant = aarch64_get_variant (inst) + 1;
+      if (variant == 2)
+         variant = 3;
+      insert_field (FLD_size, &inst->value, variant, 0);
+      break;
+

     default:
       break;
     }
     default:
       break;
     }