+bfd_boolean
+aarch64_sys_reg_supported_p (const aarch64_feature_set features,
+ const aarch64_sys_reg *reg)
+{
+ if (!(reg->flags & F_ARCHEXT))
+ return TRUE;
+
+ /* PAN. Values are from aarch64_sys_regs. */
+ if (reg->value == CPEN_(0,C2,3)
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
+ return FALSE;
+
+ /* Virtualization host extensions: system registers. */
+ if ((reg->value == CPENC (3, 4, C2, C0, 1)
+ || reg->value == CPENC (3, 4, C13, C0, 1)
+ || reg->value == CPENC (3, 4, C14, C3, 0)
+ || reg->value == CPENC (3, 4, C14, C3, 1)
+ || reg->value == CPENC (3, 4, C14, C3, 2))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
+
+ /* Virtualization host extensions: *_el12 names of *_el1 registers. */
+ if ((reg->value == CPEN_ (5, C0, 0)
+ || reg->value == CPEN_ (5, C0, 1)
+ || reg->value == CPENC (3, 5, C1, C0, 0)
+ || reg->value == CPENC (3, 5, C1, C0, 2)
+ || reg->value == CPENC (3, 5, C2, C0, 0)
+ || reg->value == CPENC (3, 5, C2, C0, 1)
+ || reg->value == CPENC (3, 5, C2, C0, 2)
+ || reg->value == CPENC (3, 5, C5, C1, 0)
+ || reg->value == CPENC (3, 5, C5, C1, 1)
+ || reg->value == CPENC (3, 5, C5, C2, 0)
+ || reg->value == CPENC (3, 5, C6, C0, 0)
+ || reg->value == CPENC (3, 5, C10, C2, 0)
+ || reg->value == CPENC (3, 5, C10, C3, 0)
+ || reg->value == CPENC (3, 5, C12, C0, 0)
+ || reg->value == CPENC (3, 5, C13, C0, 1)
+ || reg->value == CPENC (3, 5, C14, C1, 0))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
+
+ /* Virtualization host extensions: *_el02 names of *_el0 registers. */
+ if ((reg->value == CPENC (3, 5, C14, C2, 0)
+ || reg->value == CPENC (3, 5, C14, C2, 1)
+ || reg->value == CPENC (3, 5, C14, C2, 2)
+ || reg->value == CPENC (3, 5, C14, C3, 0)
+ || reg->value == CPENC (3, 5, C14, C3, 1)
+ || reg->value == CPENC (3, 5, C14, C3, 2))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
+
+ /* ARMv8.2 features. */
+
+ /* ID_AA64MMFR2_EL1. */
+ if (reg->value == CPENC (3, 0, C0, C7, 2)
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+ return FALSE;
+
+ /* PSTATE.UAO. */
+ if (reg->value == CPEN_ (0, C2, 4)
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+ return FALSE;
+
+ /* RAS extension. */
+
+ /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
+ ERXMISC0_EL1 AND ERXMISC1_EL1. */
+ if ((reg->value == CPENC (3, 0, C5, C3, 0)
+ || reg->value == CPENC (3, 0, C5, C3, 1)
+ || reg->value == CPENC (3, 0, C5, C3, 2)
+ || reg->value == CPENC (3, 0, C5, C3, 3)
+ || reg->value == CPENC (3, 0, C5, C4, 0)
+ || reg->value == CPENC (3, 0, C5, C4, 1)
+ || reg->value == CPENC (3, 0, C5, C4, 2)
+ || reg->value == CPENC (3, 0, C5, C4, 3)
+ || reg->value == CPENC (3, 0, C5, C5, 0)
+ || reg->value == CPENC (3, 0, C5, C5, 1))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
+ return FALSE;
+
+ /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
+ if ((reg->value == CPENC (3, 4, C5, C2, 3)
+ || reg->value == CPENC (3, 0, C12, C1, 1)
+ || reg->value == CPENC (3, 4, C12, C1, 1))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
+ return FALSE;
+
+ /* Statistical Profiling extension. */
+ if ((reg->value == CPENC (3, 0, C9, C10, 0)
+ || reg->value == CPENC (3, 0, C9, C10, 1)
+ || reg->value == CPENC (3, 0, C9, C10, 3)
+ || reg->value == CPENC (3, 0, C9, C10, 7)
+ || reg->value == CPENC (3, 0, C9, C9, 0)
+ || reg->value == CPENC (3, 0, C9, C9, 2)
+ || reg->value == CPENC (3, 0, C9, C9, 3)
+ || reg->value == CPENC (3, 0, C9, C9, 4)
+ || reg->value == CPENC (3, 0, C9, C9, 5)
+ || reg->value == CPENC (3, 0, C9, C9, 6)
+ || reg->value == CPENC (3, 0, C9, C9, 7)
+ || reg->value == CPENC (3, 4, C9, C9, 0)
+ || reg->value == CPENC (3, 5, C9, C9, 0))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
+ return FALSE;
+
+ return TRUE;
+}
+
+const aarch64_sys_reg aarch64_pstatefields [] =